Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.     

A Micropower CMOS-Instrumentation Amplifier

A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-zero technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4-/spl mu/m double poly process has an offset (/spl tau/) of 370 /spl mu/V, an rms input referred integrated noise (0.5 -f/sub c//2) of 79 /spl mu/V, and consumes only 21 /spl mu/W (f/sub c/ = 8 kHz, V/sub DD/ = 3 V).     

A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface

A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry-Perot etalons (each one with a different resonance cavity length), photodetectors, and circuits for readout, multiplexing, and driving a serial bus interface has been fabricated in a standard 1.6 /spl mu/m CMOS technology (chip area 3.9 /spl times/ 4.2 mm/sup 2/). The result is a chip that can operate using only four external connections (including V/sub dd/ and V/sub ss/) covering the optical range of 380-500 nm with full-width half-maximum (FWHM) = 18 nm. Frequency output and serial bus interface allow easy multisensor and multichip interfacing using a microcontroller or a personal computer. Power consumption is 1250 /spl mu/W for a clock frequency of 1 MHz.     

Analysis of heat generation and thermal lensing in erbium 3-/spl mu/m lasers

The influence of energy-transfer upconversion (ETU) between neighboring ions in the upper and lower laser levels of erbium 3-/spl mu/m continuous-wave lasers on heat generation and thermal lensing is investigated. It is shown that the multiphonon relaxations following each ETU process generate significant heat dissipation in the crystal. This undesired effect is an unavoidable consequence of the efficient energy recycling by ETU in erbium 3-/spl mu/m crystal lasers, but is further enhanced under nonlasing conditions. Similar mechanisms may affect future erbium 3-/spl mu/m fiber lasers. In a three-dimensional finite-element calculation, excitation densities, upconversion rates, heat generation, temperature profiles, and thermal lensing are calculated for a LiYF/sub 4/:Er/sup 3+/ 3-/spl mu/m laser. In the chosen example, the fraction of the absorbed pump power converted to heat is 40% under lasing and 72% under nonlasing conditions. The heat generation in a LiYF/sub 4/:Er/sup 3+/ 3-/spl mu/m laser is 1.7 and the thermal-lens power up to 2.2 times larger than in a LiYF/sub 4/:Nd/sup 3+/ 1-/spl mu/m laser under equivalent pump conditions, thus, also putting a higher risk of rod fracture on the erbium system.     

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.     

Normal optical flow measurement on CMOS APS imager

A 92/spl times/52 active pixel sensor (APS) for dense normal flow estimation is presented. The sensor combines imaging and processing on the same chip efficiently. The algorithm computes partial derivatives with respect to time and space and uses their ratio to compute normal flow velocity. The chip, which has been fabricated in a CMOS 0.5 /spl mu/m process, occupies an area of 4.5 mm/sup 2/ and consumes 2.6 mW power at V/sub dd/=5 V.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

2.1 A/mm current density AlGaN/GaN HEMT

The electrical performance of high current density AlGaN/GaN HEMTs is reported. 2 /spl times/ 75 /spl mu/m /spl times/ 0.7 /spl mu/m devices grown on sapphire substrates showed current densities up to 2.1 A/mm under 200 ns pulse condition. RF power measurements at 8 GHz and V/sub DS/=15 V exhibited a saturated output power of 3.66 W/mm with a 47.8% peak PAE.     

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.     

2 V-operated InGaP-AlGaAs-InGaAs enhancement-mode pseudomorphic HEMT

A low-voltage single power supply enhancement-mode InGaP-AlGaAs-InGaAs pseudomorphic high-electron mobility transistor (PHEMT) is reported for the first time. The fabricated 0.5/spl times/160 /spl mu/m/sup 2/ device shows low knee voltage of 0.3 V, drain-source current (I/sub DS/) of 375 mA/mm and maximum transconductance of 550 mS/mm when drain-source voltage (V/sub DS/) was 2.5 V. High-frequency performance was also achieved; the cut-off frequency(F/sub t/) is 60 GHz and maximum oscillation frequency(F/sub max/) is 128 GHz. The noise figure of the 160-/spl mu/m gate width device at 17 GHz was measured to be 1.02 dB with 10.12 dB associated gain. The E-mode InGaP-AlGaAs-InGaAs PHEMT exhibits a high output power density of 453 mW/mm with a high linear gain of 30.5 dB at 2.4 GHz. The E-mode PHEMT can also achieve a high maximum power added efficiency (PAE) of 70%, when tuned for maximum PAE.     

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Feed-forward continuous and complete polarization control with a PLZT rotatable-variable waveplate and inline polarimeter

A Pb/sub 1-x/La/sub x/(Zr/sub y/Ti/sub z/)/sub 1-x/4/O/sub 3/ (PLZT) electrooptic ceramic variable-rotatable waveplate and a compact inline polarimeter have been used to develop a fast feed-forward-controlled module for the continuous and complete conversion of polarization. This requires the control of only two parameters: the direction /spl theta/ and strength of the applied voltage V/sub 0/. Feed-forward control speed is fast, taking only 24 /spl mu/s. The chip plates were made by cutting T-shaped trenches into the four sides of a 500/spl times/400/spl times/300-/spl mu/m/sup 3/ PLZT chip and coating the trenches with electrodes. The PLZT waveplate is inserted into a 330-/spl mu/m gap between thermally expanded core fibers. The input polarization states are monitored by a newly developed compact and fast inline polarimeter, which is placed in front of the polarization controller. The optimum /spl theta/ and V/sub 0/ values for the required conversion are calculated by a computer, and the corresponding voltages are then applied to PLZT waveplate.     

GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

This paper describes a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V/sub CE,sat/ and the knee voltage V/sub k/. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) junction to suppress hole injection into the collector, which results in small V/sub CE,sat/. Collector-up configuration is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. To minimize V/sub k/, we optimized the epitaxial layer structure as well as the conditions of ion implantation into the extrinsic emitter and post-implantation annealing. The best results were obtained when a 5-nm-thick 5/spl times/10/sup 17/-cm/sup -3/-doped GaInP tunnel barrier with a 20-nm-thick undoped GaAs spacer was used at the BC junction, and when 2/spl times/10/sup 12/-cm/sup -2/ 50-keV B implantation was employed followed by 10-min annealing at 390/spl deg/C. Fabricated 40/spl times/40-/spl mu/m/sup 2/ C-up TC-HBTs showed almost zero V/sub CE,sat/ (<10 mV) and a very small V/sub k/ of 0.29 V at a collector current density of 4 kA/cm/sub 2/, which are much lower than those of a typical GaInP/GaAs HBT. The results indicate that the C-up TC-HBT's are attractive candidates for high-efficiency high power amplifiers.     

A Catalog of Low Power Loss Parameters and High Power Thresholds for Partially Magnetized Ferrites

The low power loss and high power threshold properties have been measured on a number of candidate ferrite phase-shifting materials. The low power loss is characterized by /spl mu//sub 0/', the imaginary part of the diagonal component of the permeability tensor for the completely demagnetized state. /spl mu/sub 0/' was measured from 3.0 to 16.8 GHz. The high power properties are characterized by the parallel pump threshold at a bias field correspontig to H/sub i/ /spl equiv/ 0 and to 4/spl pi/M /spl equiv/ 4/spl pi/M/sub s/. The threshold was measured between 3.0 and 16.8 GHz. For the purposes of computer calculation /spl mu//sub 0/' and h/sub crit/ were fit to an equation of the form A (/spl gamma/4/spl pi/M/sub s/ / /spl omega/)/sup N/. Translating /spl mu//sub 0/' and h/sub crit/ to /spl Delta/H/sub eff/ and /spl Delta/H/sub k/ gives the YIG plus Al as the lowest loss and lowest threshold materials followed by the Gd garnets and MgMn spinels. The Ni spinels are very Iossy.     

A 160-GHz f/sub T/ and 140-GHz f/sub MAX/ submicrometer InP DHBT in MBE regrown-emitter technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.     

Efficient tunable laser operation of Tm:KGd(WO/sub 4/)/sub 2/ in the continuous-wave regime at room temperature

Tm:KGd(WO/sub 4/)/sub 2/ is studied as a three-level laser on the /sup 3/F/sub 4/ /spl rarr/ /sup 3/H/sub 6/ transition and a tunable source in the 2-/spl mu/m spectral range, operating at room temperature. An overall tunability extending from 1790 to 2042 nm is achieved with maximum output powers of 400 mW for an absorbed pump power of 1 W. Various doping levels, pump wavelengths and polarization configurations are compared and the advantages of the monoclinic double tungstates over other Tm-hosts are outlined.     

Continuous room-temperature operation of optically pumped two-dimensional photonic crystal lasers at 1.6 /spl mu/m

In this letter continuous operation is realized from two-dimensional slab photonic crystal lasers at room temperature. The laser structure is prepared by wafer fusion of an InGaAsP MQW active layer with an AlAs layer that is wet oxidized into an Al/sub 2/O/sub 3/ layer subsequently. The incident threshold pump power at 0.98 /spl mu/m is 9.2 mW for a /spl sim/10-/spl mu/m-diameter hexagonal cavity lasing at 1.6 /spl mu/m.     

Standby power reduction using dynamic voltage scaling and canary flip-flop structures

Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-/spl mu/m, dual-V/sub T/ test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2/spl times/ higher savings than an optimal open-loop approach without loss of state.