A method to determine the sweep resistance of wire bonds for microelectronic packaging

Many kinds of gold wire and bond profiles have been used in wire bonding technology. To date, no solid experimental results have been available to guide the bond designer in the choice of a better looping system. A method is proposed for evaluating the sweep resistance of wire bonds during the transfer molding process. The wire sweep method was developed to obtain load-transverse displacement curves of wire bonds. The sweep stiffness of a wire bond is defined as the index of sweep resistance to drag during the transfer molding process, and can be evaluated on the basis of the load-transverse displacement curves. A wire bond with high sweep stiffness possesses a low wire sweep and sag for integrated circuit packaging. In this study, three types of wire bonds, Q-loop, S-loop and M-loop bonds, were examined to determine the sweep stiffness. The results showed that the Q-loop bond has the highest sweep stiffness for fixed bond spans and bond heights. For longer connections or crossing another chip in multi-chip module/three-dimensional packages, the M-loop bonds were affected significantly by their kinking numbers within a bond. The experimental results indicated that the M-loop bond has 13-75% better sweep resistance than the S-loop bond, depending on the bond span and bond height used.     

The wire sweep analysis based on the evaluation of the bending and twisting moments for semiconductor packaging

The sweep deflection of wire bond caused by compound flow during the transfer molding process can seriously result in wire crossover and shorting. To predict the sweep deflection of wire bond, a sweep deflection model based on the contributions of the bending moment and the twisting moment applied on the wire bond is proposed in this study. By analyzing the numerical and experimental results of sweep deflection, the model predicts that most sweep deflection of wire bond is caused by the twisting moment instead of the bending moment in semiconductor packaging applications. The sweep deflection percentages from the twisting moment and the bending moment depend closely on the ratio of bond height and bond span. The lower the ratio of bond height and bond span, the larger the twisting moment induced sweep deflection. A set of sweep experiments is also performed to compare with the predictions of the model. The results show that a good agreement among the proposed model predictions, the FEA numerical predictions and the wire sweep experiments.     

A theoretical study to improve wire sag of ultra-long wire bond loops for 3D/MCM packaging

An innovative theoretical model by altering cross section of gold wire is proposed to reinforce the wire sag stiffness of a wire bond that suffered low yield for the applications of 3-dimensional and multi-chip module (MCM) packaging. The flexural rigidity of a wire bond is found to be a function of the material properties in the moment of inertia of a bond wire. Suffice to say, if the moment of inertia of the bond wire can be raised, the associated sag deflection will be diminished. By manipulating the moment of inertia of the bond wire, the sag deflection of the wire bond can be regulated appropriately to avoid wire sag and even the wire sweep enigma. The ellipse-like cross section of a wire bond is applied as a numerical example to improve the wire sweep stiffness or wire sag stiffness in this study. The results show the sag deflection of a wire bond can be reduced significantly if the ellipse-like cross section is oriented in the preferred direction of flexural rigidity of a wire bond. Furthermore, a systematic study of matching design is performed to control wire sag and wire sweep for the wire bonding applications of overhang cross-stacked and step-stacked packaging. It shows that to use a single diameter of bonding wire in these complicate bonding environments of overhang stacked configurations is a favored possibility. The advantages shown from the theoretical study need to be implemented in further work in a production environment on current wire bonding equipment.     

New encapsulation development for fine pitch IC devices

The continuous reduction of chip size driven by the market demand has a significant impact on circuit design and assembly process of IC packages. Shrinking chip size and increasing I/O counts require finer bond pad pitch and bond pad size for circuitry layout. As a result, serious wire deflection during transfer molding process could make adjacent wires short, and this issue becomes more critical as a smaller wire diameter has to be applied for the finer pitch wire bonded IC devices.This paper presents a new encapsulation process development for 50 μm fine pitch plastic ball grid array package. Since reduced wire diameter decreases the bending strength of bonded wires significantly, wire deflection during molding process becomes quite serious and critical. Experiments on conventional transfer molding were conducted to evaluate wire span threshold with 23.0 μm diameter gold wire. The results show that the wire span threshold is about 4.1 mm, which is much shorter than the wire span threshold of over 5.0 mm for wire with 25.4 μm diameter. Finite element analysis shows there is a significant difference in the wire deflection between 23.0 μm gold wire and 25.4 μm gold wire diameter under the same action of mold flow. A novel encapsulation method is introduced using non-sweep solution. The wire span could be extended to over 5.0 mm with wire sweep less than 1%. Reliability tests conducted showed that all the units passed 1000 temperature cycles (−55 to 125 °C) with JEDEC moisture sensitivity level 2a (60 °C/60% relative humidity for 120 h) and 3 times reflow (peak temperature at 220–225 °C). It is believed that this solution could efficiently overcome the risk of wire short issues and improve the yield of ultra fine pitch wire bonds in high-volume production.     

Ribbed package geometry for reducing thermal warpage and wire sweepduring PBGA encapsulation

The effects of changing package shape to a ribbed geometry on thermal warpage and wire sweep of a plastic BGA (PBGA) are investigated in this paper. Three rib geometries (border, diagonal, and cross) with a variation of rib widths and thicknesses are compared with the original plane geometry. Finite element analyses of thermal warpage during the reflow process of PBGA molding with and without ribbed geometry are carried out. Numerical modeling shows that the border rib has the least thermal warpage at the reflow condition. Flow visualization was performed to study the effect of rib geometry on wire sweep, and demonstrates that the wire sweep in ribbed packages is significantly less than that in the original nonribbed package     

Low-Cost Vacuum Molding Process for BGA Using a Large Area Substrate

We have developed a new ball grid array vacuum molding process using a large area substrate, called vacuum dip compression molding (VDCM), with the aim of reducing the substrate molding cost. The VDCM method imposes less of a burden on the environment because it enables efficient use of the substrate area for packaging, increasing the proportion of the effective area on the substrate. In contrast to the transfer molding method, VDCM does not generate cull or runner waste. VDCM also has the advantage of reducing the thickness of the mold resin. It can mold packages with various thicknesses using a single mold. Using VDCM equipment, we conducted a basic evaluation of molding performance. It was confirmed that no significant wire sweep occurred even when the wire length exceeded 3 mm, indicating that VDCM is less prone to wire sweep compared to transfer molding. The prototyped fine pitch ball grid arrays had a satisfactory level of moisture sensitivity.     

多层芯片应用中的封装挑战和解决方案

The continuous growth of stacked die packages is resulting from the technology‘s ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip.The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews t6he technology requirements and challenges for stacked die packages.Foremost among these is meeting package height is 1.2mm for a single die package.For stacked die packages,two or more die need to fit in the same area.That means every dimension in the package has to decrease,including the die thickness.the mold cap thickness,the bond line thickness and the wire bond loop profile.The technology enablers for stacked die packages include wafer thinning,thin die attachment,low profile wire bonding,bonding to unsupported edges and low sweep molding.     

Design in triangle-profiles and T-profiles of a wirebond using alinkage-spring model

Different profiles of a wirebond utilizing a linkage-spring model are proposed in this paper, and loop heights are minimized in order to prevent wire sweep during molding. To analyze loop profiles, a nonquantitative, time-consuming, experimental statistical method was applied in previous studies. Although the finite element model is the most powerful tool in stress analysis, it is more complex in analyzing a large deformation as compared to the linkage-spring model. The purpose of this paper is to simulate the capillary trajectory from the first bond to the second bond stages by a linkage-spring model developed by Lo, and then to discover the proper wirebond trajectories. To meet with the gold wire properties, the transient temperature distribution along the gold wire during the bonding process is considered, Accordingly, the spring constants in a linkage-spring model are modified along the wire. Furthermore, the design rules in the looping process are defined and four examples of triangle- and T-profiles of a wirebond are also presented     

Evaluation of sweep resistance of Q Auto-Loop and Square-Loop bonds for semiconductor packaging technology

Wire sweep is a main concern in the semiconductor packaging industry. The wire bonding technology, providing versatile and reliable chip-connection method, is usually adopted for MCM and 3-D package. However, there is no (standard) approach found to determine the ability of sweep resistance for a certain bond profile in the literature. In a parallel study, the concept of sweep stiffness is defined from the slope of the load–transverse displacement curves to express sweep resistance of wire bond. In this paper, two frequently used bond profiles, the Q Auto-Loop and Square-Loop bonds, were investigated experimentally to assess the effect of bond span and height on sweep resistance. Results show that the Q Auto-Loop bond has a higher sweep resistance than the Square-Loop bond, for all wire diameters. Moreover, numerical results and proposed model predictions were performed to compare with sweep stiffness experiments. Underestimated predictions indicate the importance of bond profile characteristics to sweep stiffness values, which must be included in numerical analysis.     

High-temperature wire sweep characteristics of semiconductor package for variable loop-height wirebonding technology

This paper studies the elevated-temperature sweep characteristics of wire bond during the transfer molding process for semiconductor packages. The material properties of gold wire are obtained experimentally at various temperatures. A set of sweep experiments is also performed to acquire the sweep stiffness of wire bond for several bond spans and bond heights. The linearity of the load-transverse displacement curves from sweep experiments indicates that the ranges of the allowance bond pitch in most semiconductor packages may be within linear elasticity limits. The elastic numerical analysis may be applied to predict the sweep behavior of the wire bond. In order to predict the elevated temperature behavior of wire bond sweep, a methodology is proposed in this study. With the aids of geometry factor defined in Eq. (6) and the three drag force models, Lamb’s, Sherman’s and Takaisi’s, the predictions of the elevated-temperature sweep deflections of wire bond can be tested. The results show that the increase of the sweep deflections is more related to bond span than bond height.     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

Au线键合中"塌线"问题的研究

目前,在半导体闪存多芯片的金线键合工艺中,为满足堆叠芯片不断增加等结构需要,键合线弧要求更低、更长,制造工艺变得相对更加复杂。针对生产过程中常遇到的塌线问题,通过对金线键合工艺中线弧形成动作的过程分析,以金线弹动现象为线索,探究了生产过程中塌线问题产生的原因,并给出了相应解决方案。经过此研究,长线键合的生产工艺能力得到加强,其成果对新封装产品的研发及基板设计具有有益的参考价值。     

多排焊盘外壳封装IC金丝球焊键合技术

在多层多排焊盘外壳封装电路的引线键合中,由于键合的引线密度较大,键合引线间的距离较小,键合点间的距离也较小,在电路的键合中就需要对键合点的位置、质量、键合引线的弧线进行很好的控制,否则电路键合就不能满足实际使用的要求。文中就高密度多层、多排焊盘陶瓷外壳封装集成电路金丝球焊键合引线的弧线控制、外壳焊盘常规植球键合点质量问题进行了讨论,通过对键合引线弧线形式的优化以及采用"自模式"植球键合技术大大提高了电路键合的质量,键合的引线达到工艺控制和实际使用的要求。同时,外壳焊盘上键合的密度也得到了提高。     

Effect of misalignment on electrical characteristics of ACF joints for flip chip on flex applications

The effect of misalignment on the electrical properties of anisotropic conductive film (ACF) joints is investigated in this work. It is found that along with the increase of misalignment, the connection resistance of ACF joints increases. When the misalignment in x-direction is less than 5 μm, the increase rate of connection resistance is quite large. Then, along with the severity of misalignment, the increase rate becomes smaller. Finally, when the misalignment is close to 20 μm, the increase rate rises again. The Holm's electric contact theory is used for understanding the connection resistance variation. On the other hand, with the increase of misalignment in x-direction, the insulation resistance between ACF joints decreases. If the misalignment exceeded 10 μm, the decrease is prominent for the Ni particle ACF joints. This phenomenon can be explained by the effect of dielectric damage of the epoxy.Computer programs are also developed to calculate the variation of the probability of open and shorting after misalignment and predicate the maximum misalignment tolerance. The results show that the open and shorting probability increase abruptly after misalignment. On the view of pad parameters, the open probability is mainly related to the pad area, while the pads gap is critical to the shorting probability. Large pads gap (small pad width) can reduce the shorting probability obviously. On the other hand, enlarging the pad area by increasing pad length decreases the open probability significantly. So comparing to square shape pad, rectangle shape pad can reduce the failure probability greatly.     

引线键合应用中的无偏倒技术(英文)

无偏倒技术(NoSWEEP)是引线成型工艺过程中防止引线偏倒或偏斜的一种工艺技术。该工艺技术包含独特的材料、设备和工艺,提供了当前生产工艺便于实施的有效方法。     

引线键合应用中的无延伸技术

IntroductionToday’s semiconductor industry continuesto drive for low cost/high performance components.The challenge is to maintain the current packagingtechnology costs while enhancing componentperformance. Continued die shrinks and tighter wirebonding pitch allows assemblers to utilize currentpackage designs while reducing finished packagecosts through die design. Currently, wire bond pitchreaches 40 microns with 30um in development, andwire lengths can be longer than 300 mils. For thosefi…     

多个叠层芯片封装技术

叠层芯片封装在与单芯片具有的相同的轨迹范围之内,有效地增大了电子器件的功能性, 提高了电子器件的性能。这一技术已成为很多半导体公司所采用的最流行的封装技术。文章简要叙述了叠层芯片封装技术的趋势、圆片减薄技术、丝焊技术及模塑技术。     

集成电路封装中的引线键合技术

在回顾现有的引线键合技术之后,文章主要探讨了集成电路封装中引线键合技术的发展趋势。球形焊接工艺比楔形焊接工艺具有更多的优势,因而获得了广泛使用。传统的前向拱丝越来越难以满足目前封装的高密度要求,反向拱丝能满足非常低的弧高的要求。前向拱丝和反向拱丝工艺相结合,能适应复杂的多排引线键合和多芯片封装结构的要求。不断发展的引线键合技术使得引线键合工艺能继续满足封装日益发展的要求,为封装继续提供低成本解决方案。     

Process and design analysis for ultrafine-pitched wiresweep elimination in advanced copper heat spreader BGA package

The semiconductor device trend for increasing functionalities and performances yet with smaller overall feature sizes presents escalating obstacles to the decreasing form factor along with demanding thermal carrying capability required at the package level. To confront this compounding issue, ultrafine-pitch wirebond interconnect coupled with thermally enhanced copper heat spreader attached to the package are introduced. However, the additional copper heat spreader thickness introduced within the package challenges the design of the package's wire, its loop height, and the molding process control to prevent wire sweeping occurrences. This study investigates the impact of different ultrafine pitched wire types, wire loop designs, copper heat spreader structures, and mold material types on eliminating device short from occurring due to the wire sweeping phenomena. A full factorial experiment is performed using an active silicon device packaged in a thermally enhanced ball grid array (BGA) test vehicle. In addition, test characterization is carried out using x-ray and multiinsertions hot/cold continuity tests. Then, a detailed failure analysis is performed by package decapsulation and scanning electron microscopy/energy-dispersive x-ray (SEM/EDX) to confirm the experimental findings. In conclusion, the study finds that for an ultrafine-pitched thermally enhanced BGA package, wire type is insignificant to reduce wire shorting occurrences. However, mold material and copper heat spreader structure using an optimized wire loop design are significant factors in eliminating wiresweep shorting phenomena. This study concludes with a wirebond interconnect and heat slug design recommended along with an improved process parameters and assembly material sets found from the experiment.     

Shorting strap tunable stacked patch PIFA

An oppositely shorted dual-band stacked patch planar inverted-F antenna (PIFA) is developed. RF switches are integrated to the shorting straps of the stacked patches to make a tunable PIFA. The L band switch yields 0.45-dB insertion loss and 10-dB isolation bandwidth (BW) of 108% at 1.8 GHz. The tunable PIFA yields 10% frequency tunability BW at 745 MHz when the number of upper radiating patch's shorting straps changes and 20% BW at 1137 MHz when the number of lower radiating patch's shorting straps changes. Independent lower and upper frequency tunings are achieved through this technique.