An investigation into warpages,stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.     

Reliability prediction for TFBGA assemblies

One of the key hot topics in dense large scale integration packaging technologies is to reduce the thermomechanical stress caused by a mismatch of coefficients of thermal expansion among material employed. Nearly all manufacturers of portable electronics products perform several kinds of physical tests in the development cycle to evaluate reliability of the products. In this paper, results obtained by accelerated thermal and power cycling tests by using thin fine pitch gall grid array (TFBGA) packages are reported. Power-cycling stands for a lifetime acceleration method which is close to the real environmental conditions of many electronic products. For this purpose, a set of TFBGA thermal test packages were designed and manufactured for reliability assessment of solder joint interconnections. The assemblies consisted of an array of polysilicon resistors surrounding a sensing diode for accurate temperature measurements. The package uses a qualified bill of materials including a 36-mm/sup 2/ dummy die. Each assembly was designed to perfectly reproduce the thermomechanical behavior of the mass production packages by several semiconductor manufacturers. This package is used in telecom wireless application where it offers high density input/output solution for advanced application-specific integrated circuit (IC) devices a system on chip ICs. Both experiments and simulations were carried out to locate the position of the most critical parts. Complexity of structural package characteristics was examined by using finite-element method modeling methodology. A strain energy based model was employed to locate the most vulnerable parts in the package and predict failure rates.     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

A four-point-bending-test for the stability assessment of glass frit bonded molded microsensors

For increasingly miniaturized micromechanical sensors the silicon package is thinned and therefore more sensitive to thermomechanical stresses caused by the production stages. We present a four-point-bending-test that enables the investigation of reliability relevant loading like warping. The initiation of crack growth at the glass frit bonding frame is observed by an infrared camera and critical fracture mechanical parameters are determined for different tensile and shear mode contributions. Based on this crucial fracture mechanical data the stability of silicon packages can be assessed.     

Chip package interaction for LED packages

Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.     

The accuracy of structural approximations employed in analysis ofarea array packages

At the present time, area-array packages are a very common electronics packaging approach. One of the major concerns in designing such packages is the reliability of solder joints, die, and the various material interfaces present in the package. Currently, analytical, numerical, and experimental methods are employed in the analysis of thermo-mechanical stresses/strains in area array packages. The sources of error in these analytical and numerical models may be broadly characterized as being due to geometry representation, material behavior, solution procedure, and due to the accuracy in representing the load history. In this paper we assess the errors in package models due to geometry representation and material behavior using a representative area-array package, namely the 225 input/output (I/O) plastic ball grid array (PBGA). The package deformation due to a fixed temperature change is experimentally characterized using Moire interferometry and numerically simulated using both two- and three-dimensional finite element models. The difference in behavior between the finite element prediction and experimental results is explained using solder material behavior data available in the literature. A comparison of accuracy as well as efficiency is made between the different finite element models. Finally, conclusions are drawn on the aspects of package construction and material that influence behavior, and on the most efficient finite element model to accurately capture this behavior     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

Integrated transient thermal and mechanical analysis of molded PBGApackages during thermal shock

During thermal shock, large thermal gradients exist within a molded plastic ball grid array (PBGA) package. The conventional assumption of uniform temperature distribution becomes invalid. In this paper, an integrated thermal-mechanical analysis was performed to evaluate the transient effect of thermal shock. For comparison, an isothermal analysis was also conducted. The computational fluid dynamics (CFD) method was used to obtain the thermal boundary conditions surrounding the package. The heat transfer coefficient obtained through CFD was compared to two analytical solutions. It was found that the analytical values were not acceptable in the time period of interest. Therefore, to obtain the actual maximum die stress, CFD solution has to be used instead of analytical solutions to derive the thermal boundary condition. This boundary condition was then applied to the package and a sequentially coupled heat transfer and thermal stress analysis was performed. The transient analysis has shown that high stresses occur in the die due to thermal shock, which can not be seen under the traditional isothermal assumption. The impact of plastic ball grid array (PBGA) package parameters on transient die stress was also studied, including mold thickness and substrate thickness. The results in this paper could be applied to either wire bond or flip-chip PBGA packages     

LQFP和eLQFP热机械可靠性的有限元分析

封装形式的差异性对产品可靠性具有重要影响。基于有限元法,对比分析了薄型四方扁平封装(LQFP)和载体外露薄型四方扁平封装(eLQFP)在室温和回流焊温度下的翘曲、芯片和粘片胶的应力水平以及各材料界面应力分布。研究表明,LQFP的翘曲比eLQFP的大,但芯片和粘片胶上的最大应力无明显差别;eLQFP在塑封材料与芯片有源面界面的应力水平比LQFP的大;eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剪切应力比LQFP的大,但eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剥离应力比LQFP的小;eLQFP在塑封材料与芯片载体镀银区界面的应力水平高于LQFP的应力水平,由于塑封材料与镀银芯片载体的结合强度弱,eLQFP更易发生界面分层。     

Stress impact of moisture diffusion measured with the stress chip

The experimental observation of the actual thermo mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by the publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads.Moisture can saturate a package very fast at high temperatures and high humidity within hours but also at low temperatures and low humidity within weeks or months. Every normal stored or used package will be swelled due to this moisture. A high temperature over a short time or within the first cycle of a temperature cycling test will dry the package and the internal stress of the package decrease. This moisture swelling will be investigated in this paper.All measurements are supplemented by finite element simulations based on calibrated models for in depth analysis and for extrapolating the stress results to sites of the package that are not measured directly. The methodology of closely combining stress measurements and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time to-market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.     

Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages

In this paper we study board-level thermomechanical reliability of a wafer-level chip-scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die side, thickness of the pad on the test board, thickness of the test board, and dimension of the die. The Taguchi method along with the technique of analysis of variance are applied in the robust design process. Importance of these factors on the thermomechanical reliability of the package is ranked and the resulting robust design is further verified.     

Methodology for Modeling Substrate Warpage Using Copper Trace Pattern Implementation

The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line width and pitch. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques typically utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multilayer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.      

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

B-Spline X-Ray Diffraction Imaging — Rapid non-destructive measurement of die warpage in ball grid array packages

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging (www.itrs.net [1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die.This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 μrad ≈ 0.003° in times as short as 9–180 s (worst case X–Y spatial resolution = 100 μm) for a full 8.7 mm × 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.     

Simulating package behavior under power dissipation using uniformthermal loading

The thermomechanical behavior of electronic packages under power dissipation is simulated using uniform thermal loading. Two packages are studied, a large periphery leaded plastic quad flat pack (PQFP) package and a more compact plastic ball grid array (PBCA) package, both mounted on a printed circuit board (PCB). Experimentally verified linear elastic finite element models are used to find the displacements at the predicted failure location during power dissipation, and then during uniform thermal loading. The results for the two cases are then analyzed to find correlations between power dissipation levels and equivalent heating temperatures. One use of the results could be to replace power cycling fatigue tests with thermal cycling tests, For the packages studied, the results revealed that very little uniform heating is required to simulate the thermomechanical effects at the failure location resulting from power dissipation. Due to the prestrained state of the packages at room temperature, power dissipation decreases the expansion mismatch while increasing the thermal mismatch between package and PCB     

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration (C_sat) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.