Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

No-flow underfill flip chip assembly––an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Electrostatic Reliability Characteristics of GaN Flip-Chip Power Light-Emitting Diodes With Metal–Oxide–Silicon Submount

The electrostatic reliability characteristics of gallium nitride flip-chip (FC) power light-emitting diodes (PLEDs) with metal-oxide-silicon (MOS) submount are investigated for the first time. The electrostatic damage reliability of the reported diode submount and that of our proposed simple structure MOS submount are fabricated and compared. Their corresponding electrostatic protection capabilities are increased from 200 V (conventional PLED) to 500 V (FC-PLED on diode submount), to 500 V (FC-PLED on MOS submount with a SiO₂ thickness of 297 A?), and even to a value as high as 1000 V (FC-PLED at a SiO₂ thickness of 167 A?), which are much higher than the PLED industrial test value of 150 V at -5 V/-10 ? A criterion and are also much more robust than the previous academic reports.     

倒装焊复合SnPb焊点应变应力分析

近年来,在微电子工业中,轻、薄、短、小是目前电子封装技术发展的趋势。因此,倒装焊技术应用越来越广,而焊点的可靠性在倒装焊技术中变得越来越重要。采用有限元软件,模拟、分析了焊点高度和下填料对焊点在热载荷作用下的应力应变值。     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

Chip Scale Package (CSP) solder joint reliability and modeling

A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB). The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2-D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. A viscoelastic constitutive model was used for molding compound. Finite element models, incorporating the viscoplastic flow and evolution equations for solder and the viscoelastic equations for molding compound, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless Lead-on-Chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints while a dwell time in excess of 10 min per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between the experiment and the model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatique life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Rapid power cycling of flip-chip and CSP components on ceramic substrates

Power cycling has been done for flip-chip and CSP components solder joined onto ceramic substrates. Cycle periods as short as 1 min were applied in the experiments where the chip temperature varied between about 30°C in the power off-state and 100–150°C in the power on-state. Disconnections of the joints were found after 4000–17 000 power cycles. The flip-chip components joined onto low temperature cofired ceramic substrate showed slightly better reliability than the components joined onto alumina substrate. Most of the samples showed clear effects of deterioration of the joints seen as increasing chip temperature for power on-state. The experimental results are compared with calculations based on modified Coffin–Manson equation as well as with one-dimensional simulations.     

High-Brightness InGaN–GaN Power Flip-Chip LEDs

We report the fabrication of InGaN–GaN power flip-chip (FC) light-emitting diodes (LEDs) with a roughened sapphire backside surface prepared by grinding. It was found that we can increase output power of the FC LED by about 35% by roughening the backside surface of the sapphire substrate. The reliability of the proposed device was also better, as compared to power FC LEDs with a conventional flat sapphire backside surface.      

挠性光电印制电路板工艺光纤特性仿真与测试

挠性光电印制电路板(Flexible Electro-Optical Printed Circuit Board, FEOPCB)在高温层压制作过程中,埋入光纤会产生热应力,造成光纤损坏等缺陷,影响其可靠性和高速信号传输性能。为了降低FEOPCB弯曲半径并提升其可靠性,将在双面覆铜聚酰亚胺(PI)基板上设计制作高精度矩形光纤定位槽。首先建立有/无涂覆层光纤埋入挠性基板有限元仿真模型,对FEOPCB制造工艺进行模拟仿真,并对埋入光纤应力及影响因素进行分析。结果表明,有涂覆层光纤所受应力远小于无涂覆层光纤。针对有涂覆层光纤,采用激光刻蚀技术在双面覆铜PI基板上制作了高精度矩形定位槽,通过高温层压工艺完成了FEOPCB制作。FEOPCB完成了温度冲击、低温、高温、湿热和10万次弯曲疲劳可靠性试验,利用光学显微镜观察分析,埋入光纤无高温降解和破裂等缺陷。FEOPCB最小弯曲半径小至2 mm,弯曲损耗分别为0.57 dB (90°)和1.12 dB (180°),且相邻光纤之间无串扰,在850 nm波长条件下通信速率可达10 Gbps,误码率小于10^-16。     

Packaging properties of ALIVH-CSP using SBB flip-chip bondingtechnology

A new chip scale package (CSP) using an organic laminated substrate called μCSP was developed, which was fabricated using ALIVH substrate as a interposer and stud-bump-bonding (SBB) flip-chip technology. The ALIVH substrate is a multilayered organic substrate with inner via holes in any layer. The newly developed CSP-L using ALIVH substrate realized a miniaturization of its package size to the same as a CSP using a ceramic substrate (CSP-C). In order to perform the SBB flip-chip bonding onto the ALIVH substrate, an excellent coplanarity of the substrate surface was required. The required coplanarity was obtained using a fixture during the SBB flip-chip bonding process. The first-level packaging reliability and the second-level packaging reliability onto ALIVH mother board were evaluated. The resulting reliabilities were good enough to apply to practical use     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications

Smart labels are a new generation of low cost transponders consisting of a transponder chip and a flexible type of antenna. Applying a flip chip assembly technology yields a new generation of low cost radio frequency identification (RFID) system that is a paper-thin smart label. Anisotropically conductive adhesive (ACA) is utilized to attach a flip chip onto a paper substrate to form the BiStatix RFID tag. Unlike bar codes, which are passive tags, smart labels can dynamically transmit and receive information to help identify, track and route packages remotely. The concept of flipping or inverting a silicon chip to be mounted on a paper substrate offers distinct advantages and enables achieving the cost and performance goals of this new product technology.Significant process development and reliability assessment was required to develop this smart label application. This paper discusses the process development and reliability assessment that was completed to achieve a low cost flip chip on paper assembly process. The various characteristics of ACA made it an enabling technology for this smart label application. A bare (unbumped) flip chip––without a dielectric layer and conductive polymer bumps––was aligned and placed on the paper substrate with compressive force. A thin layer of anisotropically conductive adhesive was used to attach the IC chip to the conductive ink antenna on the paper substrate. The conductive adhesive underfills and cures in only seconds. Advantages of this environmentally preferred process include the elimination of additional curing processes and reduced equipment requirements as well as the reduction of total IC packaging thickness.     

倒装焊接在压力敏感芯片封装工艺中的研究

胶粘引丝无法实现硅压力敏感芯片的小型化封装,无引线封装可以解决该问题。倒装焊接具有高密度、无引线和可靠的优点,通过对传统倒装焊接工艺进行适当的更改,倒装焊接可应用于压力敏感芯片的小型化封装。采用静电封接工艺在普通硅压力敏感芯片上制作保护支撑硅基片,在硅压力敏感芯片的焊盘上制作金凸点,调整倒装焊接的工艺顺序和工艺参数,实现了绝压型硅压力敏感芯片的无引线封装,为压力传感器小型化开辟了一条新路。试验结果表明该封装方式可靠性高,寿命长,具有耐恶劣环境的特点。     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.