采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Change in d.c. and 1/f noise characteristics of n-submicron MOSFETs due to hot-carrier degradation

Hot-carrier stress and its influence on d.c. and 1/f noise characteristics in submicron n-channel MOSFETs was investigated. From a 0.5 μm CMOS technology we observed a negative shift in the threshold voltage and a decrease in the drain current. The degradation increases the series resistance on the drain side. In most cases, the relative 1/f noise in the drain current also increases. A degraded device is often found to be noisier in its reverse mode than in its normal mode. The novel material is that the normalized 1/f noise analysis in terms of the 1/f noise parameter α is a more sensitive diagnostic tool for hot-carrier degradation in submicron MOSFETs than S_I (

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) and some results are qualitatively explained in terms of mobility fluctuations.     

Correlation between the low-frequency noise spectral density and the static device parameters of silicon-on-insulator MOSFETs

The empirical relationship between the device transconductance and the input-referred noise spectral density observed on partially depleted SOI n-MOSFETs is examined for other types of devices. As is shown, buried-channel p-MOSFETs processed in the same 1 /spl mu/m CMOS SOI technology show the same behavior. The exponential dependence is also observed for SDI n-MOSFETs fabricated in a 3 /spl mu/m CMOS technology, strongly emphasizing the generality of the result. Furthermore, it is valid both in linear operation (weak and strong inversion) and in saturation. The physical back-ground of this correlation is further elaborated and a new relationship is derived for the noise in the subthreshold regime.<>     

Hot-carrier reliability in deep-submicrometer LATID NMOSFETs

The hot-carrier degradation of large angle tilt implanted drain (LATID) NMOSFETs of a 0.35 μm CMOS technology is analysed and compared to the degradation behaviour of standard LDD devices. LATID NMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity. By means of I–V characterisation and charge pumping measurements, the different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage.     

Hot-carrier degradation analysis based on ring oscillators

This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs I_dsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.     

Electrical noise and RTS fluctuations in advanced CMOS devices

A brief overview of recent issues concerning the low frequency (LF) noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental results obtained on advanced CMOS generations. The use of the LF noise measurements as a characterization tool of large area MOS devices is also discussed. The main physical features of random telegraph signals (RTSs) observed in small area MOS transistors are reviewed. The impact of scaling on the LF noise and RTS fluctuations in CMOS silicon devices is also addressed. Experimental results obtained on 0.18 μm CMOS technologies are used to predicting the trends for the noise figure of foregoing CMOS technologies e.g. 0.1 μm and beyond. The formulation of the thermal noise underlying the LF fluctuations in MOSFETs is recalled for completeness.     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

MAGFET based current sensing for power integrated circuit

A new on-chip non-invasive integrated current sensing, compatible with standard CMOS technology, has been developed, using a 1.2 μm BiCMOS ALCATEL technology, to sense the current in the drain side of a power MOSFET. The circuit is based on a split-drain magnetic sensor, implemented on the same chip of an integrated gate driver for a power MOSFET. A CMOS biasing circuit with a differential current output is also developed. The simulation results of the current sensing show a conversion gain of 1.25 mV/mT.     

Hot-carrier reliability of submicron NMOSFETs and integrated NMOS low noise amplifiers

The effects of hot-carrier stress (HCS) on the performance of NMOSFETs and a fully integrated low noise amplifier (LNA) made of NMOSFETs in a 0.18 μm CMOS technology are studied. The main effects of HCS on single NMOSFETs are an increase in threshold voltage and a decrease in channel carrier mobility, which lead to a drop in the biasing current of the transistors. In the small-signal model of the transistor, hot-carrier effects appear as a decrease in the transconductance and an increase of the output conductance. No clear change was observed in the parasitic gate–source and gate–drain capacitances in the devices under test due to hot carriers. The main effects of hot carriers in the LNA were a drop of the power gain and an increase of its noise figure. The input and output matching, S₁₁ and S₂₂, slightly increased after hot-carrier stress. The third- order input-referred intercept point (IIP3) of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the current–voltage (I–V) characteristics of the transistors in the LNA at the particular operating point where they were biased.     

Modeling of the body current in a Bi-MOS hybrid-mode environment

The body current I_B of deep submicron lightly doped drain pMOSFETs has been investigated. Based on the experimental results, an analytical I_B model, applicable for devices operating in a Bi-MOS hybrid-mode environment, has been developed for the first time. The proposed model is able to effectively characterize the measured I_B results over a wide range of independently applied biases (gate, drain and body) and gate lengths (from 1 μm down to 0.25 μm). The possibility of minimizing or even eliminating the undesired I_B is also explored and discussed for the first time.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Investigation on seal-ring rules for IC product reliability in 0.25-μm CMOS technology

The distance between active region and the seal-ring location has been investigated in a 0.25-μm CMOS process. From the experimental results, this distance can be shrunk to only 5 μm without increasing leakage current and decreasing ESD robustness of the ESD protection devices after reliability tests of High-Accelerated Stress Test (HAST) and Temperature Cycling Test (TCT).     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Internally matched, ultralow DC power consumption CMOS amplifier for L-band personal communications

An internally matched, extremely low operation voltage amplifier monolithic microwave integrated circuit (MMIC) has been implemented in a 0.35-/spl mu/m silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology for L-band personal communications. At 1.6 GHz the MMIC amplifier has a gain of 6.4 dB and a noise figure of 4.8 dB at a drain voltage of 0.6 V and a current of 2 mA. The MMIC amplifier exhibits a Gain/Power quotient as high as 5.33 dB/mW, which we believe is the highest recorded for Si CMOS MMIC technology.     

采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构对ＣＭＯＳ／ＳＯＩ器件和电路抗γ射线总剂量辐照特性的影响。通过与多晶硅栅器件对比进行的大量辐照实验表明,ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构不仅可以降低ＣＭＯＳ／ＳＯＩ电路的源漏寄生串联电阻和局域互连电阻,而且对ＳＯＩ器件的抗辐照特性也有明显的改进作用。     

Impact of latch phenomenon on low-frequency noise in SOI MOSFETs

The low-frequency noise in fully (FD) and partially (PD) depleted SOI MOSFETs is experimentally investigated for channel lengths down to 0.1 μm. The noise is discussed in terms of carrier number and mobility fluctuations for a wide range of SOI structures. Furthermore, the influence of the latch effect on low-frequency noise is analyzed. It is found that the flicker noise is mainly caused by the carrier number fluctuations due to the dynamic trapping of electrons (or holes) by oxide interface traps in all the SOI devices. However, an excess noise is also obtained in the presence of a parasitic bipolar action.     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits