Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input–soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%.      

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

High-throughput LDPC decoders

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length.     

Memory sub-banking scheme for high throughput MAP-based SISO decoders

The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, we present sub-banked memory implementations (both single port and dual port) of the SW SISO decoder that achieves high throughput, low decoding latency, and reduced memory energy consumption. Our contributions include derivation of the optimal memory sub-banked structure for different SW configurations, study of the relationship between memory size and energy consumption for different SW configurations and study of the effect of number of sub-banks on the throughput/decoding latency for a given SW configuration.     

A Decoding Algorithm for Turbo Product Codes Using Optimality Test and Amplitude Clipping

This paper presents an iterative soft-input/soft-output (SISO) decoderfor product code using optimality test and amplitude clipping. A modifiedexpression for computing the soft-output of SISO decoder is proposed.The correlation discrepancy is employed to provide an optimality teston the decision codeword. The optimality test is performed in rowand column decoding to evaluate the reliability of row and columndecision codewords. Based on the optimality test, the variable reliabilityfactor is introduced for optimization of turbo decoding. A stoppingcriterion with very little performance degradation is also designedfor turbo decoding of product codes by using the optimality test.Besides, the amplitude clipping is employed to improve the performanceof turbo product code. Simulation results on the performance of theintroduced SISO decoder are presented.     

LTE-Advanced标准中一种基于反向重算的低存储容量Turbo码译码器结构设计

在LTE-Advanced标准中,为满足移动环境下的低功耗要求,低存储容量的译码器结构设计引起了广泛关注.本文在分解Turbo码网格图的基础上,研究了前向状态度量的反向重算方法,提出了一种基于反向重算的低存储容量译码器结构设计方案.在Log-MAP算法下研究了一种适合反向重算的修正雅可比对数式实现方法,推导了反向重算的数学表达式,并给出了实现结构.结果表明,所涉及的反向重算译码结构,以很小的冗余计算为代价将存储容量降低了50%,译码性能非常接近Log-MAP算法,在冗余计算复杂度、存储容量和译码性能指标上具有更好的均衡性.     

A Hybrid Decoder for Block Turbo Codes

We propose a novel iterative decoder for block turbo codes (BTCs). The proposed decoder combines soft-input/softoutput (SISO) and hard-input/hard-output (HIHO) constituent decoders in order to obtain better error performance and reduce the computational complexity compared to classical BTC decoders. We show that the new decoder, called ?hybrid decoder?, offers a better complexity/performance tradeoff than a classical BTC decoder.     

Doubly Iterative Equalization of Continuous-Phase Modulation

In this paper, a doubly iterative receiver is proposed for joint turbo equalization, demodulation, and decoding of coded binary continuous-phase modulation (CPM) in multipath fading channels. The proposed receiver consists of three soft-input soft-output (SISO) blocks: a front-end soft-information-aided minimum mean square error (MMSE) equalizer followed by a CPM demodulator and a back-end channel decoder. The MMSE equalizer, combined with an a priori soft-interference canceler (SIC) and an a posteriori probability mapper, forms a SISO processor suitable for iterative processing that considers discrete-time CPM symbols which belong to a finite alphabet. The SISO CPM demodulator and the SISO channel decoder are both implemented by the a posteriori probability algorithm. The proposed doubly iterative receiver has a central demodulator coupled with both the front-end equalizer and the back-end channel decoder. A few back-end demodulation/decoding iterations are performed for each equalization iteration so as to improve the a priori information for the equalizer. As presented in the extrinsic information transfer (EXIT) chart analysis and simulation results for different multipath fading channels, this provides not only faster convergence to low bit error rates, but also lower computational complexity.     

New SISO decoding algorithms

A new maximum a posteriori (MAP)-equivalent soft-input soft-output (SISO) algorithm is derived together with its simplified versions. The proposed SISO algorithms provide a good compromise between complexity and performance. Our simplest SISO algorithm has lower complexity than the log-MAP, the max-log-MAP, and the soft-output Viterbi (1998) algorithm SISO algorithms, and it is an equivalent max-log-MAP algorithm. When this algorithm is used, turbo codes with block length as short as 150 bits will outperform convolutional codes when compared on the basis of equal decoder complexity.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.     

高存储效率的MAP译码器网格信息更新实现方法

本文提出一种新型的高存储效率的最大似然译码(MAP)译码器网格信息更新实现方法,该方法可以降低Turbo码译码器状态阵列计算对存储器的需求.利用该实现方法可以使得MAP译码器的前向网格信息和后向网格信息共享同一存储器,而且前向和后向的网格信息更新以及MAP译码产生的外部信息同时进行计算;因此该法可以提高Turbo译码的运算速度、降低存储器开销,进而降低Turbo译码电路实现时的硅片面积.     

Turbo multiuser detection for differentially modulated CDMA

In this letter, we study differentially modulated, iteratively decoded CDMA. The iterative multiuser receiver proposed consists of an additional soft-input soft-output (SISO) differential decoder, when compared to turbo multiuser detectors for absolutely modulated systems. Algorithms for iterative decoding with and without phase information at the receiver are developed. The resulting turbo receivers with differential modulation outperform coherent receivers with absolute modulation at moderate to high signal to noise ratios due to the interleaver gain associated with recursive inner encoders in serially concatenated encoding structures.     

Iterative reduced-search decoding for coded partial-response channels

The full-complexity soft-input/soft-output (SISO) detector based on the BCJR algorithm for coded partial-response channels has a computational complexity growing exponentially with channel memory length. In this letter, we propose a low complexity soft-output channel detector based on the Chase decoding algorithm, which was previously applied to decode turbo product codes. At each iteration, the proposed detector forms a candidate list using all possible combinations of bit patterns in the weakest indices based on tentative hard estimates and a priori information fed back from the outer decoder. To demonstrate the performance/complexity tradeoff of the proposed detector, simulation results over rate-8/9 turbo-coded EPR4 and ME/sup 2/PR4 channels are presented, respectively. It is shown that the proposed detector can significantly reduce the computational complexity with only a small performance loss compared to the BCJR algorithm.     

A soft-input soft-output APP module for iterative decoding ofconcatenated codes

Concatenated coding schemes consist of the combination of two or more simple constituent encoders and interleavers. The parallel concatenation known as “turbo code” has been shown to yield remarkable coding gains close to theoretical limits, yet admitting a relatively simple iterative decoding technique. The recently proposed serial concatenation of interleaved codes may offer superior performance to that of turbo codes. In both coding schemes, the core of the iterative decoding structure is a soft-input soft-output (SISO) a posteriori probability (APP) module. In this letter, we describe the SISO APP module that updates the APP's corresponding to the input and the output bits, of a code, and show how to embed it into an iterative decoder for a new hybrid concatenation of three codes, to fully exploit the benefits of the proposed SISO APP module     

Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%     

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memory blocks between all half-iterations to be removed is presented. A complexity analysis of the elementary decoder leads to a low complexity decoder architecture for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup which also includes an innovative parallel product encoder. The implemented block turbo decoder processes input data at 600 Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Some solutions to reach even higher data rates are finally presented.     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.