Electronically tunable CMOS class-AB output stage

A new technique for CMOS class-AB output stages is introduced in this Letter. The technique uses a master–slave configuration of a complementary common-source output stage. It offers the advantage that the quiescent and minimum currents of the output stage can be independently tuned. The effectiveness of the proposed technique was verified by simulations using a standard n-well 0.18 μm CMOS process with 1 V supply voltage. A voltage buffer, that includes the proposed output stage, is able to drive a capacitive load of 0.5 nF obtaining −63 dB total harmonic distortion. The topology features also power efficiency of about 63% for a pure resistive output load equal to 50 Ω.     

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC–DC buck converter

A single-inductor dual-output (SIDO) DC–DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6–5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.     

Effects of output harmonic termination on PAE and output power of AlGaN/GaN HEMT power amplifier

The authors experimentally investigate and discuss the effects of output harmonic termination on power added efficiency (PAE) and output power of an AlGaN/GaN high electron mobility transistor (HEMT) power amplifier (PA). The AlGaN/GaN HEMT PA with gate periphery of 1 mm was built and tested at L-band. Large-signal measurements and comparisons of the PAE and output power were carried out at different DC bias conditions from 50% of saturated drain current (I/sub dss/) to 1% of Id., for the PA with and without output harmonic termination. For class-AB operation at 25% of I/sub dss/, an increase of about 10% in peak PAE and 1 dBm in output power were observed in saturated output power range. Improvements of up to 9% in PAE and 1.2 dBm in output power were achieved over the measured DC bias conditions provided the output harmonics are properly terminated.     

High-drive CMOS current amplifier

A high-performance current amplifier is proposed which is based on a folded-cascode transresistance amplifier and a low-distortion class AB current output stage. The loop gain of the transresistance amplifier exhibits a gain bandwidth product of 10 MHz and a DC gain as high as 100 dB which allows accurate closed-loop operations to be achieved. Despite the intrinsic low-linearity performance of current amplifiers with respect to their voltage amplifier counterpart, the proposed circuit provides an output current of 7 mA with a total harmonic distortion (THD) better than -55 dB while requiring only 200 μA of quiescent current for the output transistors. The circuit was fabricated in a 1.2 μm CMOS process, uses a 5 V power supply, and dissipates 4 mW     

A unity power factor resonant AC/DC converter for high-frequencyspace power distribution system

This paper presents analysis and design of a resonant AC/DC converter topology, suitable for use in an advanced single-phase, sine-wave voltage, high-frequency power distribution system of the type that was proposed for a 20 kHz space station primary electrical power distribution system. The converter comprises a transformer, a double-tuned resonant network comprising of series- and parallel-tuned branches, a controlled rectifier, and an output filter. Symmetrical phase control technique that generates fundamental AC current in phase with the input voltage is employed. Steady-state analysis of the converter in continuous current mode of operation is provided, and the performance characteristics presented. The proposed converter has close-to-unity rated power factor (greater than 0.98), a wide range of output voltage control (0%-100%), low total harmonic distortion in input current (less than 8%), and high conversion efficiency. Finally, selected experimental results of a bread-board converter are presented     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

Analysis and design of a high-frequency link DC to utilityinterface using square-wave output resonant inverter

A line-current-modulated high-frequency (HF) link DC to utility interface power conditioning system using a square-wave output resonant inverter is proposed. The proposed system consists of a square-wave output HF resonant inverter, a rectifier, and a line-connected inverter (LCI). The system is modeled using the constant current model for the HF inverter and the step model for the DC link current. The operating modes, analysis, design, and experiment results are presented. It has been shown that systems operating with less than 5% line current harmonic distortion are realizable when the type II commutation scheme is used for the LCI. A typical application of the system presented is in interfacing photovoltaic arrays to utility lines     

UHF band high-efficiency linear power amplifier for mobile communication satellites

A linear MOSFET power amplifier with high efficiency and low intermodulation distortion is developed by using the harmonic control and gate bias optimising technique. An output power of 30 W at 1 dB gain compression and added efficiency of 52% are attained at an operating frequency of 835 MHz.<>     

New CMOS linear transconductor

A new transconductor is proposed which uses a bias feedback technique and has a simple configuration and a good high-frequency performance. The proposed transconductor is tunable by adjusting the bias current, and suitable for application to highly linear continuous-time filters. Experimental results show that the total harmonic distortion (THD) of the output current is less than 1% for the differential/single-ended input signals of up to 6.0 V/4.3 V (peak-to-peak) when the supply voltages are +or-5 V.<>     

Noise and power reduction in filters through the use of adjustablebiasing

A technique that enables the variation of bias currents in a filter without causing disturbances at the output is presented. Thus, the bias current can be kept at the minimum value necessary for the total input signal being processed, reducing the noise and power consumption. To demonstrate this approach, a dynamically biased log-domain filter has been designed in a 0.25-μm BiCMOS technology. The chip occupies 0.52 mm². In its quiescent condition, the filter consumes 575 μW and has an output noise of 4.4 nA rms. Signal-to-noise ratio greater than 50 dB over 3 decades of input and total harmonic distortion less than 1% for inputs less than 2.5 mA peak are achieved. The bias can be varied to minimize noise and power consumption without disturbing the output     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

Suppression of line voltage related distortion in current controlled grid connected inverters

The influence of selected control strategies on the level of low-order current harmonic distortion generated by an inverter connected to a distorted grid is investigated through a combination of theoretical and experimental studies. A detailed theoretical analysis, based on the concept of harmonic impedance, establishes the suitability of inductor current feedback versus output current feedback with respect to inverter power quality. Experimental results, obtained from a purpose-built 500-W, three-level, half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an output current total harmonic distortion (THD) some 29% lower than that achieved using output current feedback. A feed-forward grid voltage disturbance rejection scheme is proposed as a means to further reduce the level of low-order current harmonic distortion. Results obtained from an inverter with inductor current feedback and optimized feed-forward disturbance rejection show a THD of just 3% at full-load, representing an improvement of some 53% on the same inverter with output current feedback and no feed-forward compensation. Significant improvements in THD were also achieved across the entire load range. It is concluded that the use of inductor current feedback and feed-forward voltage disturbance rejection represent cost-effect mechanisms for achieving improved output current quality.     

Integrated ZCS quasi-resonant single-stage high power factorconverter

A new single phase zero-current-switched (ZCS) single stage quasi-resonant converter (QRC) for power factor correction (PFC) is proposed. The converter provides a good power factor, has tight output regulation, and low line current harmonic distortion. The proposed converter is suitable for low power level power supplies with high efficiency and tightly regulated output voltage     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

High efficiency and high fidelity analogue/digital switching mixedmode amplifier

An audio amplifier which combines the advantages of analogue and digital amplifiers is proposed. The high fidelity of an analogue amplifier and high efficiency of a digital amplifier are simultaneously achieved in one system. Experimental results show that the proposed amplifier has 0.005% total harmonic distortion and 90% power efficiency at output =50 W     

Analysis of a soft-switched PFC boost converter using analog and digital control circuits

This work presents a comparison between analog and digital (PIC16c73a) control types applied to the boost converter with a nondissipative snubber. Both control types use the bang-bang hysteresis current waveshaping control technique in order to achieve a quasi-unity power factor. The analog control applied presented a high power factor (0.998), high efficiency (92.87%), and low harmonic distortion [total harmonic distortion of current (THDI =2.84% and total harmonic distortion of current (THDV) =2.83%]. The digital control presented a high power factor (0.990), high efficiency (92.46%), and low harmonic distortion (THDI=5.09% and THDV=2.84%).     

A low noise,high power efficiency supply regulator for near-field power delivery

In order to deliver near-field electromagnetic power to a biomedical device or an RFID tag efficiently, the downlink signal is preferred to be at a high voltage level. To reduce power consumption and meet low supply requirements, it is advantageous for the remote device power supply to step-down the input voltage following rectification, typically using switch-mode regulators. The output ripple of a switched capacitor converter is inversely proportional to the filtering capacitance at the output node and switching frequency. In this paper, a hybrid DC–DC converter utilizing a switched capacitor regulator in master–slave configuration with a linear regulator is presented. Linear regulator actively cancels the switching ripple, while low frequency and DC current is provided by the switched capacitor converter. The converter is designed to receive an average input voltage of 5 Vpk from the receiver coil, with an output voltage of 2 V, and 5 mA of output current. The proposed regulator is fabricated in 0.35 μm technology. The power efficiency is measured to be 67%, with a nominal peak to peak ripple of less than 2 mV at the output.     

A novel high efficiency low ripple switched-capacitor DC/DC converter

This paper presents a new method to improve light load efficiency and minimize output ripple of switched-capacitor (SC) DC/DC converters. In order to improve light load efficiency, this paper proposes adaptive frequency modulation to scale down gate-drive losses as load current reduces. Adaptive duty cycle modulation is proposed to minimize output ripple as the converter works under different gain hopping mode. Furthermore, this work optimized switching frequency, the dead time of 2-phase non-overlapping clocks and switching transistor size for efficiency enhancement. A new compensation circuit is also proposed to make system stable. A transistor level implementation of the proposed SC converter in Chartered 0.35 μm CMOS process is provided. Measurement results shows: maximum ripple voltage is <8 mV and efficiency is up to 87%.     

Single-stage three-phase buck-boost type AC-DC converter with highpower factor

A new control process for single-stage three-phase buck-boost type AC-DC power converters with high power factor, sinusoidal input currents and adjustable output voltage is proposed. This converter allows variable power factor operation, but this work focus on achieving unity power factor. The proposed control method includes a fast and robust input current controller based on a vectorial sliding mode approach. The active nonlinear control strategy applied to this power converter, allows high quality input currents. Given the comparatively slow dynamics of the DC output voltage, a proportional integral (PI) controller is adopted to regulate the converter output voltage. The voltage controller modulates the amplitudes of the current references, which are sinusoidal and synchronous with the input source voltages. Experimental results from a laboratory prototype show the high power factor and the low harmonic distortion characteristics of the circuit