PWM digital pixel sensor based on asynchronous self-resetting scheme

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.     

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.     

Multiple integration method for a high signal-to-noise ratio readout integrated circuit

A multiple integration method is reported that greatly improves the signal-to-noise ratio (SNR) for applications with a high-resolution infrared (IR) focal plane array. The signal from each pixel is repeatedly sampled into an integration capacitor and then output and summed into an outside memory that continues for n read cycles during each period of a frame. This method increases the effective capacity of the charge integration and improves sensitivity. Because a low-noise function block and high-speed operation of the readout circuit is required, a new concept is proposed that enables the readout circuit to perform digitization by a voltage skimming method. The readout circuit was fabricated using a 0.6-/spl mu/m CMOS process for a 64/spl times/64 midwavelength IR HgCdTe detector array. The readout circuit effectively increases the charge storage capacity to 2.4/spl times/10/sup 8/ electrons and then provides a greatly improved SNR by a factor of approximately 3.     

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-/spl mu/m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more than an order of magnitude. Through varying the bias conditions on the photogate, dynamic sensitivity can be obtained to increase maximum allowable illumination level. Combining the above two operation schemes, the dynamic range of this new cell can be extended by more than 20/spl times/.     

A signal-processing CMOS image sensor using a simple analog operation

We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) /spl times/384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3/spl times/9.3 /spl mu/m/sup 2/. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply.     

Dramatic reduction of optical crosstalk in deep-submicrometer CMOS imager with air gap guard ring

A dielectric structure, air gap guard ring, has been successfully developed to reduce optical crosstalk thus improving pixel sensitivity of CMOS image sensor with 0.18-/spl mu/m technology. Based on refraction index (RI) differences between dielectric films (RI = 1.4 /spl sim/ 1.6) and air gap (RI = 1), total internal reflection occurred at dielectric-film/air-gap interface, thus the incident light is concentrated in selected pixel. Excellent optical performances have been demonstrated in 3.0 /spl times/ 3.0 /spl mu/m pixel. Optical spatial crosstalk achieves 80% reduction at 20/spl deg/ incidence angle and significantly alleviates the pixel sensitivity degradation with larger angle of incident light.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using new wiring technology, referred to as CLOSE Wiring, CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4% fill factor in a 30 /spl mu/m/spl times/30 /spl mu/m pixel, a 3.9 mm/spl times/3.9 mm image area, and a 5.5 mm/spl times/5.5 mm chip size. The charge handling capability for the 3.3 /spl mu/m wide VCCD achieves 9.8/spl times/10/sup 5/ electrons, The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with a 50 mm f/1.3 lens.<>     

Adaptive-integration-time image sensor with real-time reconstruction function

A computational image sensor is proposed in which the pixel controls its integration time to light intensity. The integration time of each pixel is selected from among several lengths of integration time and the integration time is shortened if the pixel intensity becomes saturated. Although the integration time of each pixel varies, the pixel intensity is adjusted on the sensor in real time. The dynamic range of the pixel value output from the proposed sensor is greatly widened. A prototype of 64/spl times/48 pixels has been fabricated by using 2-poly 2-metal 0.8-/spl mu/m CMOS process. The proposed sensor has simple functions for the comparison of intermediate integration value and threshold to control the integration time and nonlinear image reconstruction. Because the maximum number of the comparison-reset operations during a frame is three, one of the four integration times can be selected pixel by pixel. The circuit and layout design of the prototype which has computational elements based on column parallel architecture are described and the fundamental functions have been verified. By the experiments, it has been verified that the sensor can achieve a wide dynamic range by adapting to light.     

Crosstalk and microlens study in a color CMOS image sensor

The paper describes results of crosstalk investigations and microlens (/spl mu/-lens) scan experiments in a color CMOS image sensor with active pixel structure . The investigation of optical and electrical crosstalk was made on 7.8- and 5.6-/spl mu/m pixels by using samples with continuous shift of color filter (CF ) and /spl mu/-lens across the array. As a result of this investigation, the distribution of sensitivity inside a pixel has been determined. By using minimum crosstalk criteria, the optimum parameters of the /spl mu/-lens manufacturing process and optimum position of the /spl mu/-lens was determined. The paper presents color maps of pixel sensitivity and crosstalk criteria as well as snapshots illustrating sensitivity distribution and collection area. The paper presents spectral characteristics measured at different relative apertures (f-number) as well. The quantitative analysis of spectral responses allowed us to determine the contribution of each component to the overall crosstalk.     

A high-efficiency CMOS image sensor with air gap in situ MicroLens (AGML) fabricated by 0.18-/spl mu/m CMOS technology

The air gap in situ microlens (AGML) above-pixel sensor with 0.18-/spl mu/m CMOS image sensor technology has been successfully developed to dramatically improve the optical crosstalk and pixel sensitivity. We demonstrated excellent crosstalk diminution with the structure on small pixels. Compared with conventional 2.8 /spl mu/m square pixel, adopting the AGML can reduce the optical crosstalk up to 64%, and provide 21% in enhancement of photosensitivity at 0/spl deg/ incident angle. Furthermore, under 20/spl deg/ incident angle the optical crosstalk reduction and sensitivity enhancement are increased to 89% and 122%, respectively. Therefore, the AGML structure makes pixel size be further scaled down to less than 2.8 /spl mu/m square and maintain good performance.     

A 1.9 $e^{-}$ Random Noise CMOS Image Sensor With Active Feedback Operation in Each Pixel

A 1.9 e^- random noise CMOS image sensor has been developed by applying an active feedback operation (AFO), which uses a capacitive feedback effect to floating diffusion (FD) by a gate-source capacitance of a pixel source follower (SF), in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) technology. It is described that the AFO is suitable for CMOS image sensors with LOFIC because the design of the full well capacity and the FD can be independently optimized. The AFO theory is found to be explored to a large signal voltage in detail, as well as the conventional analysis of the capacitive feedback effect of the pixel SF for a small signal voltage. A 1/4-in 5.6- mum-pitch 640(H) times 480(V) pixel sensor chip in a 0.18-mum two-poly-Si three-metal CMOS technology achieves about 1.7 times the sensitivity with AFO compared with the case where the feedback operation is not positively used, resulting in an input-referred conversion gain of 210 muV/e^- and an input-referred noise of 1.9 e^-. A high well capacity of 130 000 e^- is also achieved.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

Normal optical flow measurement on CMOS APS imager

A 92/spl times/52 active pixel sensor (APS) for dense normal flow estimation is presented. The sensor combines imaging and processing on the same chip efficiently. The algorithm computes partial derivatives with respect to time and space and uses their ratio to compute normal flow velocity. The chip, which has been fabricated in a CMOS 0.5 /spl mu/m process, occupies an area of 4.5 mm/sup 2/ and consumes 2.6 mW power at V/sub dd/=5 V.     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

Characterization and deblurring of lateral crosstalk in CMOS image sensors

Lateral crosstalk in CMOS imaging arrays deter effective utilization of small pixel sizes (e.g., < 5.0 /spl mu/m /spl times/ 5.0 /spl mu/m) now permitted by technology scaling. A simple measurement setup for empirical characterization of lateral crosstalk in CMOS image sensors is presented. A demonstration of deblurring operations based on the obtained blur model of lateral crosstalk is also provided. Several well-known linear deconvolution filters are employed in the demonstration. The tradeoffs in sharpness restoration, high-frequency noise amplification, and the intensity clipping effect in the design of linear deblurring operation for the application of lateral crosstalk are illustrated.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

An ultra-low dark current CMOS image sensor cell using n/sup +/ ring reset

We present in this letter for the first time a new CMOS image sensor cell using n/sup +/-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing the layout arrangement, as high as 45% fill factor can be obtained. The dynamic range of this new cell can thus be improved by more than 10/spl times/ compared to a conventional cell.     

A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.