Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.     

FPGA在数字滤波器设计中的应用

介绍了FIR数字滤波器的硬件实现技术,结合Altera公司的FLEX10K系列芯片提出了实现FIR数字滤波器的硬件电路的方案,设计出一种8阶FIR数字滤波器,并且推广到16阶及32阶,以及实现滤波器的AHDL语言。基于FPGA的电路系统设计及其仿真结果表明此系统合理、可靠且满足设计要求。     

A low power 8-tap digital FIR filter for PRML read channels

This paper presents a low power 8-tap digital Fourier infrared (FIR) filter for partial response signalling with maximum likelihood (PRML) disk-drive read channels. Enhancements on power consumption and speed are achieved by adopting the row compression scheme with a proposed conditional carry selection method. The 8-tap digital FIR filter is fabricated by 0.8µm CMOS technology and occupies by 3.9mm × 1.5mm. The experimental results show that the FIR filter operates up to 180MHz and dissipates 1.4mW MHz^?1 with 3.7V power supply. It is proved that 20% power reduction is readily attainable with the proposed scheme.     

A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

This paper presents a CMOS 0.25-/spl mu/m continuous-time 6-tap FIR filter that is used as a fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter delay line is realized with a second-order low-pass filter. Simulations show that the tap delay can be tuned from 100 ps to 300 ps while keeping a constant group delay within the bandwidth of 2.1 GHz and 800 MHz correspondingly. Experimental results show that the FIR filter can successfully recover a 1-Gb/s differential digital signal that has been transmitted over a 220-inch PCB trace which causes -31.48-dB attenuation at the symbol rate frequency of 1 GHz. The measured bit error rate after equalization is less than 10/sup -12/ over a 750-ps sampling range, compared to a 10/sup -2/ bit-error rate before equalization. Also presented are the measurement results comparing the horizontal and the vertical openings of the signals before and after equalization for PCB traces with different length. The chip dissipates 45 mW from a 2.5-V supply and occupies 0.33/spl times/0.27 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.     

Charge-domain FIR sampler with programmable filtering coefficients

A charge-domain sampling technique for realization of mixed-mode finite-impulse response (FIR) filters is presented. The method is based on weighting signal current samples integrated into a sampling capacitor with a set of parallel digitally controlled current-mode switches each carrying a unit current element. The fine achievable resolution and digital controllability of the filter tap coefficients allows realization of advanced programmable FIR filtering functions embedded into high-frequency signal sampling. Circuit-level simulation results of an example 50-MHz IF-sampler with a built-in 22-tap complex bandpass sinc/sup 3/ FIR function in 0.35-/spl mu/m CMOS are shown, demonstrating the feasibility of the presented method.     

Structured design of a 288-tap FIR filter by optimized partialproduct tree compression

A compact 10-b, 288-tap finite impulse response (FIR) filter is designed by adopting structured architecture that employs an optimized partial product tree compression method. The new scheme is based on the addition of equally weighted partial products resulted from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products and the sign extension operations are manipulated independently to ensure the operation at 72 MHz, the internal clock frequency generated by the integrated phase-locked loop (PLL) clock multiplier. In addition to the optimized transmission gate full adder, modified carry save compression circuits such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. This structured approach enables cascade design that requires more than 288-tap FIR filtering. The completed 288-tap FIR fitter core occupies 5.36×7.29 mm² of silicon area that consists of 371732 transistors in 0.6-μm triple-metal CMOS technology, and it consumes only 0.8 W of average power at 3.3 V     

基于FPGA的FIR滤波器优化设计

介绍了一种在FPGA上实现的占用硬件资源少但是速度快的有限脉冲响应滤波器结构,新提出的结构不包含乘法器模块,而是采用加法器和移位寄存器替换乘法器模块。采用的方法为对乘法器系数近似为二次幂三项之和,在FPGA上实现的一个7阶有限脉冲响应滤波器表明该方法比传统含乘法器模块的滤波器占用面积减少75%。     

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.     

Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism

Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions     

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew

A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.     

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension

This paper presents four novel area-efficient field-programmable gate-array (FPGA) bit-parallel architectures of finite impulse response (FIR) filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. The key to this is a clever use of variable-depth shift registers which are efficiently implemented in Xilinx FPGAs in the form of shift register logic (SRL) components. Comparisons with the conventional architecture of FIR filter with symmetric boundary processing show considerable area saving especially with long-tap filters. For instance, our architecture implementation of the 8-tap low Daubechies-8 FIR filter achieves ~ 30% reduction in the area requirement (in terms of slices) compared to the conventional architecture while maintaining the same throughput. Two of the above-cited novel architectures are dedicated to the special case of symmetric FIR filters. The first architecture is highly area-efficient but requires a clock frequency doubler. While this reduces the overall processing speed (to a maximum of 2), it does maintain a high throughput. Moreover, this speed penalty is cancelled in bi-phase filters which are widely used in multirate architectures (e.g., wavelets). Our second symmetric FIR filter architecture saves less logic than the first architecture (e.g., 10% with the 9-tap low Biorthogonal 9&7 symmetric filter instead of 37% with the first architecture) but overcomes its speed penalty as it matches the throughput of the conventional architecture.     

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-/spl mu/ hboxm CMOS

A switched-capacitor (SC) bandpass interpolating filter is proposed with the capability of achieving, simultaneously, channel selection and frequency up-translation, together with sampling rate increase, in a multirate configuration at high frequency. This filter has been designed for efficient use in a direct-digital frequency synthesis (DDFS) system with considerable rewards in terms of speed reduction of the digital core plus the digital-to-analog converter (DAC), as well as in the relaxation of the continuous-time (CT) smoothing filter order. It exhibits a 15-tap finite impulse response (FIR), with a bandpass frequency response centered at 57 MHz and a stop-band rejection higher than 45 dB. At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-/spl mu/m CMOS technology. To implement a specific multi-notch FIR function, the filter architecture will comprise an effective low-speed polyphase-based interpolation structure with autozeroing capability, high-speed SC circuitry with fast opamps, and also ultra-low timing-skew multiple phase generation in order to achieve high-performance operation at high frequency. The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3. It consumes 2 mm/sup 2/ of active silicon area, 120 mW (analog) and 16 mW (digital) power, with a single 2.5-V supply, which corresponds to 8.6 mW of analog power per zero.     

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision     

基于分布式算法的高阶FIR滤波器及其FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

一种基于迭代短卷积算法的低复杂度并行FIR滤波器结构

该文基于快速卷积算法,提出一种适用于线性相位FIR滤波器的并行结构。该结构采用快速卷积算法减少子滤波器个数,同时让尽可能多的子滤波器具有对称系数,然后利用系数对称的特性减少子滤波器模块中的乘法器数量。对于具有对称系数的FIR滤波器,提出的并行结构能够比已有的并行FIR结构节省大量的硬件资源,尤其当滤波器的抽头数较大时效果更明显。具体地,对一个4并行144抽头的FIR滤波器,提出的结构比改进的快速FIR算法(Fast FIR Algorithm, FFA)结构节省36个乘法器(14.3%),23个加法器(6.6%)和35个延时单元(11.0%)。     

A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering

A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mum CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm² of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm² of die area and 0.02 mW of power per tap.     

高速FIR滤波器的流水线结构

通过一个13阶线性相位的平方根升余弦滚降FIR数字滤波器的结构设计，介绍了如何应用流水线技术来设计高速FIR滤波器。考虑到FPGA的容量问题，对采用流水线技术之后的FIR滤波器占用的硬件资源进行了分析，得出一些结论。     

Theory and factorization for a class of structurally regular biorthogonal filter banks

Regularity is a fundamental and desirable property of wavelets and perfect reconstruction filter banks (PRFBs). Among others, it dictates the smoothness of the wavelet basis and the rate of decay of the wavelet coefficients. This paper considers how regularity of a desired degree can be structurally imposed onto biorthogonal filter banks (BOFBs) so that they can be designed with exact regularity and fast convergence via unconstrained optimization. The considered design space is a useful class of M-channel causal finite-impulse response (FIR) BOFBs (having anticausal FIR inverses) that are characterized by the dyadic-based structure W(z)=I-UV/sup /spl dagger//+z/sup -1/UV/sup /spl dagger// for which U and V are M/spl times//spl gamma/ parameter matrices satisfying V/sup /spl dagger//U=I/sub /spl gamma//, 1/spl les//spl gamma//spl les/M, for any M/spl ges/2. Structural conditions for regularity are derived, where the Householder transform is found convenient. As a special case, a class of regular linear-phase BOFBs is considered by further imposing linear phase (LP) on the dyadic-based structure. In this way, an alternative and simplified parameterization of the biorthogonal linear-phase filter banks (GLBTs) is obtained, and the general theory of structural regularity is shown to simplify significantly. Regular BOFBs are designed according to the proposed theory and are evaluated using a transform-based image codec. They are found to provide better objective performance and improved perceptual quality of the decompressed images. Specifically, the blocking artifacts are reduced, and texture details are better preserved. For fingerprint images, the proposed biorthogonal transform codec outperforms the FBI scheme by 1-1.6 dB in PSNR.     

A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines