An integrated readout circuit for personal dosimetry with phase-shift compensation technique to improve stability

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35 μm CMOS technology. It occupies an area of 2.113×0.81 mm². Measurement results show that the proposed channel can process up to 1 MHz counting rate and provide a conversion gain of about 170 mV/fC at a power dissipation of 330 μW with a 3.3 V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays.     

Power efficient asynchronous multiplexer for X-ray sensors in medical imaging analog front-end electronics

This paper presents a new power efficient asynchronous multiplexer (MUX) for application in analog front-end electronics (AFE) used in X-ray medical imaging systems. Contrary to typical synchronous MUXes that have to be controlled by a clock, this circuit features a simple structure, as the clock is not required. The circuit dissipates power only while detecting the active signals and then automatically turns back to the power down mode. Medical imaging systems usually consist of several dozen to even several hundreds of channels that operate asynchronously. The proposed MUX enables an unambiguous choice of the active channel. In case of two or more channels that become active at the same time the MUX serializes the reading out data from particular channels. This characteristic leads to 100% effectiveness in data processing and no impulses’ loss. The proposed MUX together with an experimental readout ASIC has been implemented in the CMOS 0.18 μm process and occupies 1100 μm²/channel area. It works properly in a wide range of the voltage supply in between 0.8 and 1.8 V. Energy consumed during the detection of one active channel is below 1 pJ, while the detection time is about 1 ns.     

FGMOS based voltage-controlled resistor and its applications

The paper presents floating gate MOSFET (FGMOS) based low-voltage tunable resistor operating at supply voltages of ±0.75 V. The proposed circuit is then used as basic building block to develop tunable negative resistor, current-mode divider, and variable transresistance amplifier. The circuit is simple, compact, and accurate. The total power dissipation of the proposed circuit is 18.6 μW. The circuits are simulated to demonstrate the effectiveness using SPICE in 0.5-μm CMOS technology.     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

0.5 V bulk-driven analog building blocks

Basic analog building blocks, such as voltage follower (VF), second generation Current Conveyor (CCII), and Current Feedback Operational Amplifier (CFOA), capable for operating under 0.5 V supply voltage, are introduced in this paper. The input stage of the proposed blocks is based on bulk-driven pMOS devices, and simultaneously offers the advantages of almost rail-to-rail input/output voltage swing and capability for operation under the extremely low supply voltage. Their performances have been evaluated and compared through simulation results using a standard 0.18 μm n-well process. The bandwidth of the voltage and current followers for both CCII and CFOA is 11 MHz and 10 MHz, respectively. The power consumption of CCII and CFOA is 30 μW and 50 μW, respectively.     

Low-voltage FGMOS based analog building blocks

Novel floating gate MOSFET (FGMOS) based low-voltage analog circuits such as current-to-voltage converter, current-mode divider and pseudo-exponential function generator are proposed in this paper. The inherent advantages of these circuits are their simplicity, accuracy and low power dissipation. The current-to-voltage converter is operated with a single power supply of 0.9 V. The current-mode divider and pseudo-exponential function generator are operated at supply voltages of ±0.9 V. It was observed that the power dissipation of the current-to-voltage converter is reduced to 12 μW using a single power supply. The power dissipations of the current-mode divider and pseudo-exponential function generator are found to be 356 and 471 μW, respectively. The proposed circuits are simulated using SPICE in 0.5 μm CMOS process technology to demonstrate the feasibility and the effectiveness of the proposed circuits.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

CMOS WTA maximum and minimum circuits with their applications to analog switch and rectifiers

This paper presents design of a voltage-mode multiple-inputs winner-take-all (WTA) maximum (max) and minimum (min) circuits. The proposed circuits are realized in a CMOS technology with low-component counts of transistors. They display usability of the proposed building block, where the maximum bandwidth of voltage follower is around 1 GHz and low-delay time is around 1.5 ns with high-input and low-output impedances. The THD obtained is around 0.8% within the 0.6Vp−p input range. The power dissipation of the proposed circuits is obtained to be around 0.62 mW with ±1.25 V power supplies. In applications, half-wave and full-wave rectifiers and analog switch are included. Computer simulation results by using SPICE program with TSMC 0.25 μm are carried out to show the performance of the proposed WTA max and min circuits, rectifiers and analog switch. In addition, the sample layout of the max circuit occupies an area of around 798 μm² and post-layout simulation results are exhibited to concrete the pre-layout simulation results.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.     

Low cost bulk-silicon CDMOS technology and enhanced dv/dt high voltage driver circuit for PDP data driver IC

In this paper, a 256-channel data driver IC for plasma display panels (PDPs) is proposed. A new low cost 0.5 μm bulk-silicon CDMOS (CMOS and DMOS) technology is developed, resulting in the improvement of input data frequency up to 120 MHz and reduction of die cost about 20% compared with the conventional one. A novel high voltage driver circuit is also presented to optimize dv/dt of the output signal from 1.2 to 0.2 V/ns. The proposed circuit can avoid unwanted turning on of the pLEDMOS transistors in output stage and cut down the power dissipation by 12% compared with the conventional one. The application results show rising and falling times of the output stage are 45 and 84 ns, respectively.     

Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate

The Substitution box (S-Box) forms the core building block of any hardware implementation of the Advanced Encryption Standard (AES) algorithm as it is a non-linear structure requiring multiplicative inversion. This paper presents a full custom CMOS design of S-Box/Inversion S-Box (Inv S-Box) with low power GF (2⁸) Galois Field inversions based on polynomial basis, using composite field arithmetic. The S-Box/Inv S-Box utilizes a novel low power 2-input XOR gate with only six devices to achieve a compact module implemented in 65 nm IBM CMOS technology. The area of the core circuit is only about 288 μm² as a result of this transistor level optimization. The hardware cost of the S-Box/Inv S-Box is about 158 logic gates equivalent to 948 transistors with a critical path propagation delay of 7.322 ns enabling a throughput of 130 Mega-SubBytes per second. This design indicates a power dissipation of only around 0.09 μW using a 0.8 V supply voltage, and, is suitable for applications such as RFID tags and smart cards which require low power consumption with a small silicon die. The proposed implementation compares favorably with other existing S-Box designs.     

An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of −19.7 dBm to obtain a bit-error rate (BER) of 10⁻¹². The complete receiver consumes a total power of approximately 155 mW from a 3.3-V supply. The core circuit area is 0.85×1.32 mm².     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

A high-speed current conveyor based current comparator

In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA.     

A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230×400 µm².     

Design of micropower class AB transconductors: A systematic approach

A systematic design approach to achieve micropower class AB CMOS transconductors is presented. It includes techniques to get rail-to-rail operation and continuous transconductance tuning, based on floating and Quasi-Floating Gate transistors. Application of the proposed design approach leads to a new family of high-performance power-efficient class AB CMOS transconductors. To illustrate the feasibility of this approach, 12 transconductors derived from this common framework have been designed and fabricated in a 0.5 μm CMOS technology. Measurement results show THD values for 2 V inputs of −56 dB for a static power of 300 μW and silicon area <0.07 mm².     

Solution processed inverter based on zinc oxide nanoparticle thin-film transistors with poly(4-vinylphenol) gate dielectric

An enhancement-load inverter using bottom-gated ZnO nanoparticle thin-film transistors and a polymer gate dielectric is demonstrated. The deposition of the ZnO active layer is done by spin coating of a colloidal dispersion and is hence cost-effective. Since the maximum process temperature is 200 °C, the presented device is furthermore suitable for plastic substrates. Although hysteresis is observed, the inverter shows reasonable transfer characteristics with a gain of up to 5.5 V/V at a supply voltage between 10 V and 15 V, whereas the static power dissipation is lower than 6 μW.