A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

SOS MOSFET two-dimensional analysis

Two-dimensional analysis of short-channel SOS MOSFET's is presented, The analysis is based on the circular-field-line approximation to determine the boundary conditions in the sapphire substrate. Si-sapphire interface-state effects are taken into account. Using this analysis method, short-channel SOS MOSFET characteristics were investigated. The electric-field lines, originating from the drain, are terminated not only in the Si substrate charge but also in the interface states. The interface states can suppress the short-channel effects in either n- or p-channel SOS MOSFET's. Predicted characteristics agree with the experimental results.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

An analysis of the concave MOSFET

The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.     

A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

Analysis and modeling of dual-gate MOSFET's

Dual-gate MOS transistors (both as discrete devices and as circuit elements are extremely attractive for a variety of applications where electronic gain control capability, low feedback parameters, low noise and cross modulation, reduced short-channel effects, or high breakdown voltage are required. In this paper, the operation and physical characteristics of dual-gate MOSFET's are investigated. An accurate model is developed, which enables the simulation of behavior of the device with respect to bias conditions, by means of a simple iterative algorithm. Using this model, the static characteristics are analyzed in detail, special emphasis being directed toward the properties of the drain conductance and transconductances in the various operational modes. Second order effects, not taken into account in the model, are discussed. The boundaries of the operating regions also are calculated by means of simple analytic models. Extensive experimental verification is made through measurements conducted on various dual-gate transistor structures fabricated by a shadowed-gap/lift-off process.     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Channel edge doping (CED) method for reducing the short-channel effect

A new fabrication process for short-channel MOSFET's, the channel edge doping method (CED), is proposed. In this method, highly doped regions are self-aligned with the channel edges by using a silicon dioxide liftoff technique. The spread of source/drain depletion-regions toward the channel is suppressed by the highly doped regions. Thus the short-channel effect can be prevented. Using the CED method, n-channel MOSFET's with effective channel length down to 0.9 µm are fabricated. Their characteristics are compared with those for conventionally processed MOSFET's and the effect of the CED method for reducing the short-channel effect is confirmed.     

Measurement of MOSFET substrate dopant profile via inversionlayer-to-substrate capacitance

In this paper, a new method for extracting substrate dopant concentration profile of short-channel MOSFET's is presented. It is based on the measurement of the small-signal capacitance between the inversion layer and the substrate. The method achieves effective deep depletion through dc reverse bias on the inversion-to substrate junction and thus avoids the problems with transients associated with pulsed C-V of MOS capacitors. By using transistors of different drawn lengths the effect of lateral extension of drain and source junction depletion regions is also accounted for     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Modeling of 0.1-µm MOSFET on SOI structure using Monte Carlo simulation technique

Simulation of a 0.1-µm MOSFET's characteristics using the Monte Carlo method is introduced in this paper. The studied device is a 0.1-µm MOSFET on an ultrathin nearly intrinsic SOI structure that is thought to be useful to suppress short-channel effects. To carry out the calculation, intravalley scattering with acoustic phonon and intervalley inelastic scattering have been taken into account in our model. Surface roughness scattering has also been considered in a particle manner using a classical model, which is a combination of both specular reflection and diffused scattering. In order to take the avalanche breakdown phenomena into account, a two-carrier many-particle Monte Carlo method has been used here. We proposed a new model for the impact ionization probability, and also for the velocity distribution of both the primary electron and the generated electron-hole pairs in this paper.     

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.     

Hysteresis I-V effects in short-channel Silicon MOSFET's

Hysteresis in Ids-Vdscharacteristics is observed at high drain voltages in short-channel silicon MOSFET's biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.     

Flat-band voltage dependence on channel length in short-channel threshold model

This paper describes a modified short-channel threshold model that incorporates the flat-band voltage dependence on the channel length. Results obtained from the threshold voltage measurement on n-channel MOSFET's before and after total dose radiation are in good agreement with the proposed model.     

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as Vthlowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.     

Effects of injection resistance on the performance of very-short-channel MOSFET's

Injection resistance, the spreading resistance due to current crowding at the source end of an FET channel, can lead to considerable performance reduction in short-channel MOSFET's. A simple technique for determining the magnitude of this resistance by means of measurements in the linear operation region is described. A simple analytical model which incorporates the effects of both velocity saturation and injection resistance is also developed. The method and model are experimentally verified by determination of the effects of injection resistance on MOSFET's with channel lengths from 0.2 to 24.6 µm.     

Design of ion-implanted MOSFET's with very small physical dimensions

This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.     

深亚微米MOSFET阈值电压模型

文章在分析短沟道效应和漏致势垒降低(DIBL)效应的基础上,通过引入耦合两效应的 相关因子,建立了高k栅介质MOSFET阈值电压的器件物理模型。模拟分析了各种因素对阈值电 压漂移的影响,获得了最佳的k值范围。     

An improved analytical solution of energy balance equation forshort-channel SOI MOSFET's and transverse-field-induced carrier heating

This paper presents a method for solving the one-dimensional (1-D) energy balance equation for fully depleted short-channel SOI MOSFET's. This method takes the exact kinetic energy into account and provides a new analytical solution for the non-saturated drain current region. The carrier temperature for spatially homogeneous case is described as a function of the longitudinal electric field and the carrier concentration deviation. The electron temperature is higher than that predicted by old models, which is examined by the two-dimensional simulation. The experimental data on gate current characteristics in short-channel SOI nMOSFET's can be physically interpreted by the proposed 1-D model