MBE生长的具有高β,f_T,和f_(max)值的Si/SiGe HBT

Si/SiGe异质结双极晶体管(HBT)已通过采用MBE生长一完整的层结构而制作成功。典型的基区杂质浓度为2×10~(19)cm~(-3),这远远地超过发射区的杂质浓度,结果薄层电阻为1kΩ/□左右。器件显示500V Early电压,室温下最大的电流增益为550,77K下上升到13000。制作在掩埋层衬底上的器件,其f_(max)为40GHz,这是已报道的Si/SiGe HBT的最大值。特征频率达42GHz,这是采用MBE生长的这类晶体管的最高值。     

Measurement of collector-base junction avalanche multiplicationeffects in advanced UHV/CVD SiGe HBT's

This paper presents measurements of the avalanche multiplication factor (M-1) in SiGe HBTs using a new technique capable of separating the avalanche multiplication and Early effect contributions to the increase of collector current with collector-base bias, as well as allowing safe measurements at practical current densities. The impact of collector doping, current density, Ge profile, and operation temperature are reported for the first time using measured and simulated results from a production quality UHV/CVD SiGe HBT technology. Limitations of the technique in the presence of significant self-heating are discussed. By turning on the secondary hole impact ionization, we revealed the difference in impact ionization between strained SiGe and Si in the presence of the “dead space” effect. Despite its smaller bandgap, the compressively strained SiGe layer shows an apparent decrease in the secondary hole impact ionization rate compared to Si     

Neutral base recombination and its influence on the temperaturedependence of Early voltage and current gain-Early voltage product inUHV/CVD SiGe heterojunction bipolar transistors

We present the first comprehensive investigation of neutral base recombination (NBR) in ultra-high vacuum/chemical vapor deposited (UHV/CVD) SiGe heterojunction bipolar transistors (HBT's), and its influence on the temperature characteristics of Early voltage (V_A ) and current gain-Early voltage product (βV_A). We show that a direct consequence of NBR in SiGe HBT's is the degradation of V_A when transistors are operated with constant-current input (forced-I_B) as opposed to a constant-voltage input (forced-V_BE). In addition, experimental and theoretical evidence indicates that with cooling, V_A in SiGe HBT's degrades faster than in Si bipolar junction transistors (BJT's) for forced-I_B mode of operation. Under the forced-V_BE mode of operation, however, SiGe HBT's exhibit a thermally-activated behavior for both V_A and βV_A, in agreement with the first-order theory. The differences in V_A as a function of the input bias and temperature for SiGe HBT's are accurately modeled using a modified version of SPICE. The performance of various practical SiGe HBT circuits as a function of temperature, in the presence of NBR, is analyzed using this calibrated SPICE model     

基区不均匀重掺杂对Si/SiGe/Si HBT基区渡越时间的影响

由于发射结（ＥＢ结）价带存在着能量差ΔＥｖ,电流增益β不再主要由发射区和基区杂质浓度比来决定,给ＨＢＴ设计带来了更大的自由度。为减小基区电阻和防止低温载流子冻析,可增加基区浓度。但基区重掺杂导致禁带变窄,禁带变窄的非均匀性产生的阻滞电场使基区渡越时间增加,退桦了频率特性,特别是在低温下更为严重。     

Dual junction GaInP/GaAs solar cells grown on metamorphic SiGe/Si substrates with high open circuit voltage

Dual junction GaInP/GaAs solar cells have been grown and fabricated on Si substrates using relaxed, compositionally graded SiGe buffer layers that provide a nearly lattice-matched low threading dislocation Ge surface for subsequent cell growth. The dual junction cells on SiGe/Si displayed high open circuit voltages in excess of 2.2 V, compared to 2.34 V for control cells on GaAs, that are consistent with maintaining the 1.8/spl times/10/sup 6/ cm/sup -2/ threading dislocation density throughout the cell structure. Even with total current output limited by large grid coverage and high reflectance, total area AM1.5G efficiency is 16.8%, with active area efficiency at 18.6%. The high V/sub oc/ establishes that SiGe metamorphic buffers are viable for integrating III-V multijunction cells on Si in a monolithic process.     

The influence of carbon on the properties of Si/SiGe heterostructures

Si/SiGe/SiGe:C/SiGe/Si heterostructures are investigated by Raman spectroscopy, electroreflectance method, and secondary-neutral mass spectrometry. It is shown that doping of a SiGe layer lying between undoped SiGe layers with C (1.5%) leads to almost complete stress relaxation in the doped layer. It is found that high-temperature photon annealing is responsible for a partial stress relaxation in the lower SiGe buffer layer. However, such annealing increases the Si content in this layer. Low-temperature treatment in the radio-frequency (RF) hydrogen plasma leads to considerable stress relaxation in the lower buffer layer without varying its composition. The results obtained from the electroreflectance and secondary-neutral-mall spectra correlate with the Raman spectroscopy data.     

Reduction of p+-n+ junction tunneling currentfor base current improvement in Si/SiGe/Si heterojunction bipolartransistors

The authors report a three-order-of-magnitude reduction in parasitic tunneling current at heavily doped p⁺-n⁺ Si/Si and SiGe/Si junctions grown by rapid thermal epitaxial chemical vapor deposition (CVD) compared with previously reported results in Si junctions fabricated by ion implantation. These results demonstrate the high quality of the epitaxial interface. The low tunneling currents allow higher limits to transistor base and emitter doping levels, yielding higher gains, reduced bias resistances, and higher Early voltages for scaled bipolar devices as well as Si/SiGe/Si heterojunction bipolar transistors     

Fabrication and current-drive of SiGe/Si 'Micro-origami' epitaxial MEMS device on SOI substrate

A micromirror structure with SiGe/Si heteroepitaxial layer on a silicon-on-insulator (SOI) substrate using a 'Micro-origami' technique has been successfully fabricated. The micromirror is supported by two curved hinge structures. The device is driven by application of a current, and net angular displacements larger than 10/spl deg/ (static) and 30/spl deg/ (in resonance) were obtained. These values are comparable with or even larger than the reported values for other MEMS optical switches or beam scanning devices. The experimental results suggest that the movement is evoked by a thermal effect. The Micro-origami device has advantages of low operation voltage smaller than 2 V, and structural compatibility with the Si or SiGe LSIs.     

基于PWM的电流源/电压源的设计与分析

基于PWM技术设计的电流源/电压源的电路,采用固态继电器作为分流器,可将数安至数百安范围内变化的电流源转换成热耗小、输出电压稳定的电压源.该电源特别适合作为高电压侧测量系统的供电电源.本文对电路的工作原理、关键技术进行了分析,给出了实验结果.     

Interdigitated pn junction device with novel capacitance/voltage characteristic, ultralow capacitance and low punch-through voltage

The first demonstration of the recently disclosed channelling diode is reported. The structure combines important and unique features which can be used for a large variety of applications. The diode exhibits a novel capacitance/voltage characteristic; large capacitance variations (1 pF) have been achieved over a small voltage range. Operated as a PIN diode the device has an ultralow capacitance (0.05 pF) and a low punch-through voltage (2?3 V). This small capacitance is largely independent of the detector area and of the doping of the layers. These features are important for ultralow noise PINFET receiver applications.     

Hot electron and hot hole degradation of UHV/CVD SiGe HBT's

We investigate the degradation in current gain and low-frequency noise of SiGe HBT's under reverse emitter-base stress due to hot electrons (forward-collector stress) and hot holes (open-collector stress). Contrary to previous assumptions we show that hot electrons and hot holes with the same kinetic energy generate different amounts of traps and hence have a different impact on device degradation. These results suggest that the accuracy of using forward-collector stress as an acceleration tool and reliability predictor must be carefully examined. We also present, for the first time, the effect of Ge profile shape on the reliability of SiGe HBT's, as well as discuss measurements on SiGe HBT's as a function of device geometry and temperature     

与Si 工艺兼容的Si/ SiGe/ Si HBT 研究

我们对Si/SiGe/Si HBT及其Si兼容工艺进行了研究,在研究了一些关键的单项工艺的基础上,提出了五个高速Si/SiGe/Si HBT结构和一个低噪声Si/SiGe/Si HBT结构,并已研制成功台面结构Si/SiGe/Si HBT和低噪声Si/SiGe/Si HBT,为进一步高指标的Si/SiGe/Si HBT的研究建立了基础。     

The influence of defects on device performance of MBE-grown Si homojunction and strained Si1-xGex/Si heterostructures

Different Si homojunction and strained Si_1-xGe_x/Si heterojunction diodes and bipolar transistors have been fabricated by Si-MBE. The effect of annealing on Si homojunction diodes and transistors are studied. It is found that annealing generally improves the Si device performance, such as the ideality factor and breakdown characteristics. The influence of⁶⁰Co γ irradiation on the Si_1-xGe_x/Si diode performances are investigated by studying the temperature dependence of their electrical characteristics, and the results are correlated with the quality of the MBE-films. γ irradiation causes a drop in material conductivity due to the generation of atom-displacement defects in the whole volume of the wafers and increases the defect density at hetero-interfaces. The forward I-V curves of Si_1-xGe_x/Si devices may shift towards lower or higher voltages, depending on the film quality and the irradiation dose. The increase of defect density in strained Si_1-xGe_x/Si films appears to occur easier for the films with lower quality. Electrical measurements and calculations show that the defect-associated tunneling process is important in current transport for these MBE grown Si homojunction and strained Si_1-xGe_x/Si heterojunction devices, which have initially medium film quality or have been treated by irradiation.     

基于RST的SiGe/Si"或非"逻辑器件研究

文中通过利用耗尽层阻断沟道的方法,讨论了一种基于RST结构原理实现"或非"逻辑功能的器件结构.     

Effect of collector voltage and collector current on junction temperature

Experiments have been carried out on the 2N929 transistor to investigate the effect of collector voltage and collector current on junction temperature. The results indicate that at constant power dissipation increasing the collector voltage will increase the junction temperature and give the apparent effect of a higher thermal resistance.     

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.     

Optimization of characteristics related to the emitter-base junction in self-aligned SEG SiGe HBTs and their application in 72-GHz-static/92-GHz-dynamic frequency dividers

Characteristics related to the emitter-base junction of self-aligned selective-epitaxial-growth SiGe heterojunction bipolar transistors (HBTs) were optimized for use with a highly-doped base. The thickness of the Si-cap layer affected both the emitter-base junction concentration and space-charge width, so the dc and ac characteristics of the SiGe HBTs were in turn dependent on this thickness. With a 4/spl times/10/sup 19/-cm/sup -3/ boron-doped base, a 131-GHz cutoff frequency and ECL gate-delay time of 5.4 ps were achieved for the optimized SiGe HBTs. A static frequency divider with a maximum operating frequency of 72.2 GHz and a dynamic frequency divider with a maximum operating frequency of 92.4 GHz were developed for optical-fiber link and millimeter-wave communication systems of the future.     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.     

A comparison of thin film microrefrigerators based on Si/SiGe superlattice and bulk SiGe

Most of the conventional thermal management techniques can be used to cool the whole chip. Since thermal design requirements are mostly driven by the peak temperatures, reducing or eliminating hot spots could alleviate the design requirements for the whole package. Monolithic solid-state microcoolers offer an attractive way to eliminate hot spots. In this paper, we review theoretical and experimental cooling performance of silicon-based microrefrigerators on a chip. Both Si/SiGe superlattice and also bulk SiGe thin film devices have been fabricated and characterized. Direct measurement of the cooling along with material characterization allows us to extract the key factors limiting the performance of these microrefrigerators. Although Si/SiGe superlattice has larger thermoelectric power factor, the maximum cooling of thin film refrigerators based on SiGe alloys are comparable to that of superlattices. This is due to the fact that the superlattice thermal conductivity is larger than bulk SiGe alloy by about 30%.