Low-voltage low-power CMOS RF low noise amplifier

In this paper, a 1 V, 2 GHz CMOS low-noise amplifier (LNA) was developed intended for use in the front-end receiver. The circuit is simulated in standard $0.25\mathrm{\mu }\mathrm{m}$ CMOS MOSIS. The LNA gain is 25.675 dB, noise figure (NF) is 4 dB, reverse isolation $(S_{12})$ is $-134.3\mathrm{dB}$, input return loss $(S_{11})$ is $-14.6\mathrm{dB}$, output return loss $(S_{22})$ is $-13.34\mathrm{dB}$, and the power consumption is 5.13 mA from a single 1 V power supply. One of the features of the proposed design is using a three-component cascode limitation, one of it is a transistor, to reduce the supply voltage.     

低功耗宽带CMOS低噪声放大器

本文实现了一款低功耗的宽带低噪声放大器(LNA)。该低噪放由输入级、中间级和输出级组成。由于每一级都采用了电流复用技术,显著地降低了功耗。输入级通过电阻、电容负反馈和并联电感,实现了良好的输入匹配。引入电感抵消了电容产生的虚部阻抗并且抵消了电容产生的极点。与电阻负反馈放大器相比,本文提出的结构提高了增益。中间级通过并联电感引入零点,采用低Q值拓展带宽。输出级是源级跟随器,提供了良好的输出匹配。经0.18 μm TSMC CMOS工艺仿真验证,在3 V的电源电压下,功耗仅为4.89 mW。另外在1~4.5 GHz频带范围内,电压增益(S21)为14.8±0.4 dB,噪声系数(NF)介于3.1~4.2 dB之间,输入、输出反射系数(S11、S22)均小于-10 dB。在4GHz时,输入三阶交调点(IIP3)达到-11dBm。     

CMOS多频段低噪声放大器设计

近年来,随着无线通信技术的蓬勃发展,可兼容多种移动通信系统标准的新一代移动终端的研究正逐渐成为热点.要实现多频段的移动终端接收系统,需要解决的首要问题就是如何实现位于该系统第一级的低噪声放大器LNA的多频段化.传统的方法是将多个单频段的LNA并联起来使用,但会造成较大的功耗,占用较大的芯片面积,增加成本,而且随着接收标准的不断增多,该方法最终将不可行;另外一种实现多频段的方式是采用开关式LNA,但其只能工作于一个频段下,当希望能同时工作于多个频段时,该方法也将不适用;还可以采用宽带LNA来实现多个频段的放大,但同时也会放大其他频段的干扰信号.     

运用级间并联电感的级联CMOS低噪声放大器的优化设计

本文介绍了一种运用级间并联电感优化CMOS低噪声放大器的设计方法。传统的级联低噪声放大器可以从两级级联放大器的角度出发,视为共源级和共栅级的级联,由于共栅极的极好的隔离性,两级放大器可以分别设计。理论分析表明：在共源极和共栅极间引入级间匹配网络,即并联一个电感加强两极间的耦合,可以有效的改善低噪放的功率增益和噪声性能。文章最后用一个工作于5GHz的低噪放的设计实例,验证了理论分析的正确性。     

26-42 GHz SOI CMOS low noise amplifier

A complementary metal-oxide semiconductor (CMOS) single-stage cascode low-noise amplifier (LNA) is presented in this paper. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator (SOI) technology. All impedance matching and bias elements are implemented on the compact chip, which has a size of 0.6 mm /spl times/ 0.3 mm. The supply voltage and supply current are 2.4 V and 17 mA, respectively. At 35 GHz and 50 /spl Omega/ source/load impedances, a gain of 11.9 dB, a noise figure of 3.6 dB, an output compression point of 4 dBm, an input return loss of 6 dB, and an output return loss of 18 dB are measured. The -3-dB frequency bandwidth ranges from 26 to 42 GHz. All results include the pad parasitics. To the knowledge of the author, the results are by far the best for a silicon-based millimeter-wave LNA reported to date. The LNA is well suited for systems operating in accordance to the local multipoint distribution service (LMDS) standards at 28 and 38 GHz and the multipoint video distribution system (MVDS) standard at 42 GHz.     

Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure

This paper presents a single ended low noise amplifier (LNA) using 0.18 μm CMOS process packed and tested on a printed circuit board. The LNA is powered at 1.0 V supply and drains 0.95 mA only. The LNA provides a forward gain of 11.91 dB with a noise figure of only 2.41 dB operating in the 0.9 GHz band. The measured value of IIP3 is 0.7 dBm and of P1dB is −12 dBm. Zhang Liang is currently with Cyrips, Singapore. Ram Singh Rana was born in Delhi (India). Having primary education in Bijepur, Dwarahat(India), he received the B.Tech. (hons.) degree in Computer Engineering from G.B. Pant University, Pantnagar, India in 1988 and the Ph.D degree from the Indian Institute of Techonology (IIT), Delhi, India in 1996. He worked for his Ph.D in the Centre for Applied Research in Electronics, IIT Delhi in close interaction with the Semiconductor Complex Limited, Mohali, India. He was with ESPL, Mohali(India) in 1988 for a very short period and then served IIT Delhi as Senior Research Associate (88-90) and Senior Scientific Officer (90-95) where his main contributions were on CMOS analog IC design in subthreshold operation. He was a Lecturer in the Kumaon Engg. College, Dwarahat (India) before serving the IIT Roorkee (Formerly Univ. of Roorkee) in 1998 as assistant Professor. In 1999, he was a Manager (Engineering), Semiconductor Product Sector of the Motorola, Noida, India. Since joining the Institute of Microelectronics, Singapore in 2000, he worked mostly on RFICs, Fractional-N PLLs, ADCs. During 2001-2004, he worked there as IC Design Research and Training Program Manager. Currently, he is serving the institute as Senior Research Engineer in CMOS IC design (below 1V) for biomedical and bio-sensors. His current interests include design and consultancy for CMOS ICs/systems for the biomedical and high speed communication applications. Dr. Rana received Young Teacher Career Award from the All India Council for Technical Education in 1997. He was an Adjunct Asstt. Professor with the National University of Singapore (NUS), Singapore in 2004. He is sole inventor of two US granted patents and has filed several other patents. He has authored/co-authored about 40 publications. He has been reviewer for several IEEE journals and conference papers. Dr Rana is a senior member of IEEE and a member of Graduate Program in BioEngineering, NUS Singapore. He has chaired /co-chaired sessions in many international conferences. Zhang Liang was born in China in June 1978. He received the Bachelor degree and the Master degree in Electrical Engineering from the Xi’an JiaoTong University, Xi’an, China, in 2000 and 2003 respectively. Since 2003, he has been a postgraduate student in the Electrical and Computer Engineering department, National University of Singapore(NUS), Singapore and has successfully completed M.Engg degree program of the NUS. He is currently working on RFICs as a design engineer in Cyrips, Singapore. His design and research interests include integrated circuit design for communications. He has authored/co-authored several publications of international standard. Hari K Garg obtained his BTech degree in EE from IITDelhi in 1981. Subsequently, he obtained his MEng & PhD degrees from Concordia University in 1983 & 1985, and MBA from Syracuse University in 1985. He was a faculty member at Syracuse University from 1985 till 1995. He has been with the National University of Singapore since 1995 till present with the exception of 1998-1999 when he was with Philips. Hari’s research interests are in the area of digital signal/image processing, wireless communications, coding theory and digital watermarking. He has published extensively on these and related topics. He is also founder of several companies in the space of mobile telephony. In his spare time, Hari enjoys singing and a good game of Squash.     

A 1.5-V, 1.5-GHz CMOS low noise amplifier

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices     

一种CMOS卫星导航接收机多模低噪声放大器设计

本文介绍了一种用于卫星导航接收机中的多模低噪声放大器模块的设计.采用主流CMOS工艺,对源极负反馈的共源共栅放大器的放大管栅源两极间增加可调电容、调整偏置电压、共用片外匹配以及调整输出电感的方法,实现多个频点的噪声和功率匹配.采用TSMC 0.18μm 1P4M射频CMOS工艺进行流片验证,在1.207GHz到1.575GHz频段多个频点处的可获得17.3dB到18.5dB增益,在1.8V工作电压下,噪声系数均小于1.8dB,工作电流均小于3.6mA,完全满足接收机的应用.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

60 GHz compact low noise amplifier in 65 nm CMOS

A single-ended low noise amplifier in 65 nm CMOS for applications at 60 GHz is presented. Its measured gain and noise figure at the centre frequency of 57 GHz are 19.1 dB and 5.5 dB, respectively, and it provides wideband matching. Transistors in the design have an asymmetrically fingered layout which reduces parasitic capacitances while simultaneously allowing for higher channel current densities.     

CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

A highly linear CMOS low noise amplifier for K-band applications

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

0.18-um CMOS 3.1-10．6GHz超宽带低噪声放大器设计

介绍了一种基于0．18-um CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器。在3．1～10．6GHz的频带范围内对它仿真获得如下结果：最高增益12dB；增益波动小于2dB；输入端口反射系数S11小于-10dB；输出端口反射系数S22小于-15dB；噪声系数NF小于4．6dB。采用1．5V电源供电，功耗为10．5mW。与近期公开发表的超宽带低噪声放大器仿真结果相比较，本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点。