An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

A 0.6-V Low Power UWB CMOS LNA

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

A 1.5-V 2–9.6-GHz Inductorless Low-Noise Amplifier in 0.13-μm CMOS

This paper presents an inductorless low-noise amplifier (LNA) design for an ultra-wideband (UWB) receiver front-end. A current-reuse gain-enhanced noise canceling architecture is proposed, and the properties and limitations of the gain-enhancement stage are discussed. Capacitive peaking is employed to improve the gain flatness and -3-dB bandwidth, at the cost of absolute gain value. The LNA circuit is fabricated in a 0.13-mum triple-well CMOS technology. Measurement result shows that a small-signal gain of 11 dB and a -3-dB bandwidth of 2-9.6 GHz are obtained. Over the -3-dB bandwidth, the input return loss is less than -8.3 dB, and the noise figure is 3.6-4.8 dB. The LNA consumes 19 mW from a low supply voltage of 1.5 V. It is shown that the LNA designed without on-chip inductors achieves comparable performances with inductor-based designs. The silicon area is reduced significantly in the inductorless design, the LNA core occupies only 0.05 mm², which is among the smallest reported designs.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm²     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

3.6~4.7GHz低噪声放大器

以一种经典的窄带低噪声放大器结构为基础,分析级联放大器的S参数,通过优化元件参数,获得了一种在3.6~4.7 GH z范围内具有低输入回波损耗、低噪声系数的放大器。采用标准的0.18μm RF CM O S工艺进行了设计和实现。芯片面积为0.6 mm×1.5 mm。测试结果表明:在3.6~4.7 GH z的范围内,该宽带低噪声放大器输入回波损耗小于-14 dB;噪声系数小于2.8 dB,增益大于10 dB。在1.8 V电源下功耗约为45 mW。     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

Design of Full Band UWB Common-Gate LNA

A two-stage, common-gate in cascade with cascode, ultra wideband low noise amplifier (LNA) topology is proposed for 3.1 to 10.5 GHz full band application. The common-gate first stage is adopted and optimized for low noise figure (NF) at high frequencies. The LNA implemented in 0.18 mum CMOS shows more than 10 dB input return loss, maximum gain of 16 dB, and NF of 3.8~4.0 dB over the full frequency band while dissipating 5.3 mA from 1.8 V supply.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

A Packaged and ESD-Protected Inductorless 0.1–8 GHz Wideband CMOS LNA

In this letter, an inductorless 0.1-8 GHz wideband CMOS differential low noise amplifier (LNA) based on a modified resistive feedback topology is proposed. Without using any passive inductors, the modified resistive feedback technique implemented with a parallel R-C feedback, an active inductor load, and neutralization capacitors achieves high gain, low noise, and good return loss over a wide bandwidth. To ensure the robustness in the system integration, electro-static discharge diodes are added to the radio frequency pads. The LNA was fabricated using a digital 90 nm CMOS technology. It achieves a 3 dB bandwidth of 8 GHz with a 16 dB voltage gain, noise figures from 3.4 dB to 5.8 dB across the whole band, and an input third-order intermodulation product (IIP3) of -9 dBm. The active area of the chip is 0.034 mm². The chip was packaged and tested on an FR4 PCB using the chip-on-board approach.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.