Gate-oxide breakdown accelerated by large drain current inn-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 μm, gate width-15 μm) occurs in ~100 s at an applied gate oxide field of ~5.2 MV/cm during the high drain current stress, while it occurs in ~100 s at an applied gate oxide field of ~10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method     

Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Lifetime modeling of intrinsic gate oxide breakdown at high temperature

High resolution time-dependent dielectric breakdown tests are carried out on 7.2 nm gate oxide capacitors (n-type) in the electric field range 8.3–13.2 MV/cm at high temperatures (160–240 °C). It is proven that even at these high temperatures log(t_BD) is proportional to 1/E_OX and the time-to-breakdown mechanism matches the anode hole injection (AHI) model (1/E_OX model). In addition it is presented that the TDDB activation energy E_a for this type of gate oxide has linear dependence on stress electric oxide field.     

Effect of hot-carrier injection on n- and pMOSFET gate oxideintegrity

N- and pMOSFETs with 9-nm gate oxide are compared. Injected hot holes are about 100 times as effective as electrons at 10.5 MV/cm of oxide field in causing oxide breakdown. Gate current in nMOSFETs under stress conditions is due to holes and electrons. The gate current in pMOSFETs is about 1000 times as large, but solely due to electrons. PMOSFETs can tolerate 1000 times more charge injection than nMOSFETs, but not more drain current stress     

Time-dependent dielectric breakdown of SiO2 films in a wide electric field range

We have performed time dependent dielectric breakdown measurement of SiO₂ films in the electric field (E_OX) range 7–13.5 MV/cm and evaluated the electric field dependence of intrinsic lifetime, using both area and temperature dependences of oxide lifetime. We have evaluated the electric field dependence of time to breakdown (t_BD) below 125°C, because the activation energy of intrinsic lifetime changes at 125°C t_BD of 7.1 and 9.6 nm oxides is not proportional to exp(E_OX) but proportional to exp(1/E_OX). This suggests that the breakdown mechanism of 9.6 and 7.1 nm oxides is the same and adheres to the anode hole injection model. However, the breakdown mechanism of 4.0 nm oxides is not the same as that of 7.1 and 9.6 nm oxides. The slope of log(t_BD) versus 1/E_OX plot in 4.0 nm oxide increases with decreasing oxide fields. The intrinsic lifetime in the positive gate bias decreases with increasing oxide thicknesses in the range of electric fields employed in the present experiment.     

Ultra-thick gate oxides: charge generation and its impact on reliability

In this work, degradation and breakdown characteristics of ultra-thick gate oxides (T_ox: 50–150 nm) used in power MOS devices is investigated. Measurements indicate, that in addition to charge generation via Fowler–Nordheim tunneling, a second mechanism becomes dominant in ultra-thick gate oxides even at moderate electrical fields (i.e. 7–8 MV/cm). The results suggest, that impact ionization and related electron–hole pair creation by energetic electrons is responsible for the experimental observations. The impact of these results on the interpretation of lifetime extrapolations from accelerated tests will be discussed.     

Correlation between oxide breakdown and defects in SiC wafers

A correlation between gate oxide breakdown in metal oxide semiconductor (MOS) capacitor structures and structural defects in SiC wafers is reported. The oxide breakdown under high applied fields, in the accumulation regime of the MOS capacitor structure, is observed to occur at locations corresponding to the edge of bulk structural defects in the SiC wafer such as polytype inclusions, regions of crystallographic misorientation, or different doping concentration. Breakdown measurements on more than 50 different MOS structures did not indicate any failure of the oxide exactly above a micropipe. The scatter in the oxide breakdown field across a 10 mm × 10 mm square area was about 50%, and the highest breakdown field obtained was close to 8 MV/cm.     

Field and temperature dependence of TDDB of ultrathin gate oxide

The results of an investigation of time-dependent breakdown (TDDB) of intrinsic ultrathin gate oxide are presented for a wide range of oxide fields 4.6ox<10.4 MV/cm at elevated temperatures. It was found that TDDB of ultrathin oxide follows the E model down to 4.6 MV/cm. The data show that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. The data also show that the TDDB activation energy for this type of gate oxide is linearly dependent on oxide field. In addition, we show that the field acceleration parameter γ decreases as temperature increases     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

Electrical conduction mechanism in high-dielectric-constant ZrO2 thin films

The electrical conduction mechanism in zirconium oxide (ZrO₂) thin films as a function of temperature T and electric field E was studied. Al/ZrO₂/p-Si metal–insulator–semiconductor (MIS) capacitors were fabricated. With the Al electrode biased negative, the conduction mechanism in the electrical field of 0.81 MV/cm < E < 1.40 MV/cm and in the temperature range of 375 K < T < 450 K is found to be modified Schottky emission. The intrinsic barrier height between Al and ZrO₂ is 1.06 eV. At higher electrical fields of 1.50 MV/cm < E < 2.25 MV/cm and higher temperatures of 375 K < T < 450 K, the electrical conduction is dominated by modified Poole–Frenkel emission. The extracted trap barrier is 0.83 eV. With the Al electrode biased positive, the conduction mechanism is found to be Schottky emission at the electrical field 0.20 MV/cm < E < 0.60 MV/cm and higher temperature range of 425 K < T< 450 K. The barrier height between Si and ZrO₂ is 1.0 eV. Based on these results, an energy band diagram of the Al/ZrO₂/p-Si system is proposed.     

The effect of electrode material on the electrical conduction of metal-Pb(Zr0.53Ti0.47)O3-metal thin film capacitors

The electrical conduction of metal–PZT–metal thin-film capacitors depends on the electrode material due to the different magnitudes of the work functions. In this work, Au/PZT/Pt and Pt/PZT/Pt capacitors were fabricated and their electrical properties compared. At the low temperature range of 300–375 K, the electrical conduction of Au/PZT/Pt capacitor is space-charge-limited current (SCLC), whereas Pt/PZT/Pt capacitor shows ohmic conduction at low field (<0.55 MV/cm) and Frenkel–Poole emission at higher fields (0.55 MV/cm). The current level of Au/PZT/Pt is much lower than that of Pt/PZT/Pt at low field (<0.4 MV/cm) due to the larger barrier height for holes of Au/PZT. At high temperatures (375–450 K), the conduction mechanism of Au/PZT/Pt capacitor changes to Schottky emission, whereas that of Pt/PZT/Pt capacitor remains the same as in low temperatures of 300–375 K. The energy band diagrams of the Au/PZT/Pt and Pt/PZT/Pt systems are constructed to explain the different current–voltage characteristics.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Application of high-quality SiO/sub 2/ grown by multipolar ECR source to Si/SiGe MISFET

A 5 nm-thick SiO/sub 2/ gate was grown on an Si (p/sup +/)/Si/sub 0.8/Ge/sub 0.2/ modulation-doped heterostructure at 26 degrees C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field >12 MV/cm and fixed charge density approximately 3*10/sup 16/ cm/sup -2/. Leakage current as low as 1 mu A was obtained with the gate biased at 4 V. The MISFET with 0.25*25 mu m/sup 2/ gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.<>     

Silicon dioxide deposited by ECR-PECVD for low-temperature Si devices processing

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (E_w). Higher E_w at room deposition temperature (RT) shows low defects densities (<7 pinhole/mm²) ensuring low-temperatures process integration on large area. From FTIR analysis and Thermal Desorption Spectroscopy we also evaluated very low hydrogen content if compared to conventional rf-PECVD SiO₂ deposited at 350 °C. Electrical properties have been measured in MOS devices, depositing SiO₂ at RT. No significant charge injection up to fields 6–7 MV/cm and average breakdown electric field >10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N₂. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 10¹¹ cm⁻² eV⁻¹. These results show that a complete low-temperatures process can be achieved for the integration of SiO₂ as gate insulator in polysilicon TFTs on plastic substrates.     

Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.