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1.
The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 μm by 5 μm and a current density of 100 A/cm2 has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized 相似文献
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Athanasios Stefanou Georges Gielen 《Analog Integrated Circuits and Signal Processing》2010,65(2):185-195
This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict
the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates
substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular,
the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators
in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent
and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based
on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion
tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and
the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended
to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved
converters in the presence of substrate noise. 相似文献
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A novel clock distribution concept based on inband phase-modulated pilot insertion is demonstrated.This method avoids the need for an ultrafast phase comparator and a phase-locked loop in the receiver.Experimental results show that the clock can be successfully extracted from 160Gbit/s optical time-division multiplexing (OTDM) data signal and employed for demultiplexing of 40Gbit/s tributaries.The in-band clock distribution introduces 1.5dB of power penalty with an error-free performance. 相似文献
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New design techniques for implementing a data and clock recovery circuit on a silicon NMOS monolithic IC employing 1-μm feature sizes, and operating at speeds greater than 2 Gbit/s are described. A clocked comparator can resolve a 60-mV peak-to-peak signal into logic levels at 2 Gbit/s. The circuit can tolerate a 100° phase margin between the incoming signal and the clock. An NRZ data rate of 4 Gbit/s may be resolved by two such multiplexed circuits following a preamplifier in the same technology. A VCO capable of operation at 2 GHz in a PLL, that does not require off-chip components, is also described. An observer loop concept is employed in the PLL to align the recovered clock signal with the incoming data. 相似文献
7.
A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock
signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch
stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the
latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power
supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage
difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.
In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator
is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after
calibration. 相似文献
8.
Joonhee Kang Gupta D. Kaplan S.B. 《Applied Superconductivity, IEEE Transactions on》2002,12(3):1848-1851
A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz 相似文献
9.
A Josephson comparator based on a nonhysteric one-junction superconducting quantum interference device (SQUID) for use in a periodic-threshold A/D (analog-to-digital) converter is discussed. Simulations show that a 4-bit A/D converter using this comparator could have a sampling rate of >20 GHz with an analog signal bandwidth of >10 GHz. This performance represents a factor-of-greater-than-five improvement over that of other periodic-threshold A/D converters, which are based on two- or three-junction SQUIDs 相似文献
10.
The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW. 相似文献
11.
An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation 相似文献
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文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素(时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等),基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。 相似文献
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The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter. 相似文献
16.
《Solid-State Circuits, IEEE Journal of》1975,10(6):392-399
Describes a monolithic circuit consisting of an array of 8 voltage comparators, a resistive voltage divider, and associated logic circuits. Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage. A Gray-code output minimizes the problem of comparator indecision. The principal error sources are an asymmetry-induced comparator offset with 2-mV standard deviation and a thermally induced offset of a much as /spl plusmn/2.5 mV, dependent on signal history. The quantizer has been incorporated in an experimental 6-bit 200 megasample/s (MS/s) A/D converter. 相似文献
17.
Wennekers P. Novotny U. Huelsmann A. Kaufel G. Koehler K. Raynor B. Schneider J. 《Solid-State Circuits, IEEE Journal of》1992,27(10):1347-1352
A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V 相似文献
18.
A CMOS subranging analog-to-digital converter (ADC) incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal ill-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADC's with differential inputs and significantly better than those with single-ended inputs. The typical maximum differential nonlinearity is ±0.4 LSB, and the maximum integral nonlinearity is ±0.55 LSB without trimming or calibration. With an ADC power of 55 mW plus an SHA power of 20 mW from a 5-V supply, the active area is 1.6 mm2 in a 0.5-μm double-poly, double-metal CMOS technology 相似文献
19.
A comparator, fabricated in a 1.5 V/0.12 mum CMOS process, is presented. The commonly separated reset and active-load transistors of typical comparators are combined. In the input part two NMOS transistors are added to reduce power consumption. At a supply voltage of 0.5 V the comparator works at a maximal clock of 600 MHz and consumes 18 muW 相似文献