Channels That Heat Up

This paper considers an additive noise channel where the time-A; noise variance is a weighted sum of the squared magnitudes of the previous channel inputs plus a constant. This channel model accounts for the dependence of the intrinsic thermal noise on the data due to the heat dissipation associated with the transmission of data in electronic circuits: the data determine the transmitted signal, which in turn heats up the circuit and thus influences the power of the thermal noise. The capacity of this channel (both with and without feedback) is studied at low transmit powers and at high transmit powers. At low transmit powers, the slope of the capacity-versus-power curve at zero is computed and it is shown that the heating-up effect is beneficial. At high transmit powers, conditions are determined under which the capacity is bounded, i.e., under which the capacity does not grow to infinity as the allowed average power tends to infinity.     

A Subthreshold Low Phase Noise CMOS LC VCO for Ultra Low Power Applications

A subthreshold low power, low phase-noise voltage controlled oscillator (VCO) is demonstrated in a commercial 0.18 mum CMOS process. In subthreshold regime, MOS drain current is dominated by diffusion mechanism resulting in a high ratio of transconductance to drain current and suppressed phase noise. Therefore, low power and low phase noise characteristics are achieved without using nonconventional high passive components. The VCO measures a phase noise of -106 dBc/Hz at 400 kHz offset from 2.63 GHz oscillation frequency with 0.43 mW power dissipation drawn from 0.45 V power supply. Figures of merit for this VCO (power-frequency-normalized of 12 dB and power frequency-tuning-normalized of -10 dB) are among the best reported for CMOS oscillators.     

内置功率驱动的A3980型步进电机控制器及其应用

A3980是Allegro公司推出的一款易操作、内置功率驱动的步进电机驱动器,利用该电路来控制步进电机具有低噪声、低功耗和高精度等优点.文中对A3980的主要特点、引脚功能及应用做了详细介绍.     

Low-Noise, Low Power Dissipation GaAs Monolithic Broad-Band Amplifiers

Low-noise, low dc power dissipation GaAs monolithic amplifiers have been developed for use in VHF-UHF mobile radio systems. The developed amplifiers have two-stage constuction, where gate width for the first stage is 1000 µm, and for the second stage is 500 pm. Using this circuit configuration, both noise figure and bandwidth have been improved. To maintain the uniformity for the ion-implanted active layers and to reduce gate-source resistance R/sub S/ and gate-drain resistance R/sub D/, the "closely spaced electrode FET" was adopted. The FET enables low drain voltage operation, resulting in low dc power dissipation. The developed amplifier for the FET threshold voltage VT= --0.6 V provides a 3-dB noise figure, less than 170-mW dc power dissipation, 9-MHz-3.9-GHz bandwidth with 16-dB gain. It can operate under a unipolar power source. When external choke inductors were introduced for the amplifier, 120-mW dc power dissipation has been achieved. It has also been demonstrated that the amplifier for V/sub T/= --0.6V, which is inferior to the amplifier for VT= -2.7V regarding gain-bandwidth product and power efficiency under the same dc power dissipation, however, has an acceptable performance for use in the mobile radio systems.     

无线局域网接收机用频率综合器的关键技术

对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC 0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC 0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.     

Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed.      

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.     

低噪声、低功耗CMOS电荷泵锁相环设计

设计了一种 1 .8V、0 .1 8μm工艺的低噪声低功耗锁相环电路 ,其采用 CSA(Current Steer Amplifier)架构的压控振荡器 (VCO)。整个电路功耗低 ,芯片面积为 1 60 μm× 1 2 0 μm,对电源和衬底噪声抑制能力强。经过Spice模拟表明 ,在有电源噪声的情况下 ,输出 5 0 0 MHz时钟时周对周抖动小于 41 ps,功耗为 2 .8m W,最终与芯片的量测结果基本一致     

两相步进电机驱动器A3992及其应用

A3992是美国Allegro公司的一种串行控制步进电机驱动器,该驱动器能方便地实现两相步进电机的细分驱动,而且控制系统具有低噪声、低功耗和高精度等优点.详细介绍了A3992的主要特点、引脚功能、工作原理及典型应用电路.     

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.      

Noise suppression in a common-gate UWB LNA with an inductor resonating at the source node

In this paper, a noise suppression circuit is proposed and investigated by using resonance technique at the source. Resonance in the source node of the common-gate structure blocks the noise path while transferring the signal from input to output. Through proper analysis, a common gate structure with an active load is improved. As a result, a complementary common gate structure is introduced. A complementary common-gate structure with resonance in the source node can overcome the trade-off between noise and gain in the first stage. Hence, this structure is optimum in terms of the trade-off between gain and noise as well as power dissipation and linearity. Finally, a very-low-noise amplifier is implemented by this method and the post-layout simulation results are obtained: average power gain: 15.8 dB, minimum noise figure: 1.7 dB, bandwidth: 3.1–4.8 GHz, power dissipation of two stage: 11.28 mW, 1-dB compression point at input power: −4.67 dBm, and IP3 at input power: 8.32 dBm.     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.     

Microwave noise performance of AlGaN-GaN HEMTs with small DC power dissipation

We report low microwave noise performance of discrete AlGaN-GaN HEMTs at DC power dissipation comparable to that of GaAs-based low-noise FETs. At 1-V source-drain (SD) bias and DC power dissipation of 97 mW/mm, minimum noise figures (NF/sub min/) of 0.75 dB at 10 GHz and 1.5 dB at 20 GHz were achieved, respectively. A device breakdown voltage of 40 V was observed. Both the low microwave noise performance at small DC power level and high breakdown voltage was obtained with a shorter SD spacing of 1.5 /spl mu/m in 0.15-/spl mu/m gate length GaN HEMTs. By comparison, NF/sub min/ with 2 /spl mu/m SD spacing was 0.2 dB greater at 10 GHz.     

功能磁共振数据结构性噪声分析

本文提出了一种非参数化功能磁共振数据噪声分析方法.该方法根据噪声时域特性将其分为结构性噪声和非结构性噪声两类,它们对统计检验功效造成的影响在文中分别进行了讨论.使用正则相关分析提取数据中的结构性信号,利用基于降阶自回归模型的surrogate检验从结构性信号中确定出神经响应信号;利用随机化方法在保持非结构性噪声能量不变的情况下消除它们时域中的自相关性,使得非结构性噪声谱低频部分的能量下降.利用神经响应信号和经过随机化处理后的非结构性信号重构数据.重构数据基本满足了多种统计推断方法中白噪声的假设.构造了2种仿真数据,使用基于多窗口谱估计的F检验来验证算法的有效性.最后用此方法处理了20组真实的功能磁共振数据,成功提取到了一些在未降噪数据中检测不到的任务相关脑功能区.     

Noise–Power Optimization of Incremental Data Converters

Incremental data converters (IDCs) are useful in instrumentation and measurement applications, where low-frequency analog signals need to be converted into digital form with high accuracy and low power dissipation. They are particularly well suited for applications where a single analog-digital converter is multiplexed between many channels. This paper proposes an exact design methodology for IDCs, which optimizes the signal-to-noise ratio of the converter under practical design constraints. The process also allows the designer to apportion the noise budget in an arbitrary manner between thermal and quantization noise. The design process is illustrated by an example which describes the optimization of a third-order multiplexed IDC.     

Low standby leakage 12T SRAM cell characterisation

In this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.     

The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications

In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the first structure, the control voltage is employed to the gate of PMOS transistors which are inserted in series with the input PMOS transistors. In this case the minimum power dissipation is gained. Since the control voltage is injected to the PMOS transistors parallel with input transistors, the better tuning range in higher frequency and lower phase noise is achieved. In order to make a tradeoff between the tuning range, phase noise and power dissipation, the PMOS transistors activated with the control voltage are applied to the oscillator in both the series and parallel paths. In improved structure, the oscillator works in 2.65–13.93 GHz under 1 V supply voltage in 65 nm CMOS technology. The phase noise is −94.33 dBc/Hz at 1 MHz offset from 3.7 GHz center frequency, while the power dissipation is 328.6 μW and the chip area is 139.5 µm².     

Low power LNA using the MOSFETs in moderate inversion

This paper presents an integrated complementary metal oxide semiconductor (CMOS) low power low noise amplifier (LNA) for global positioning system (GPS) receivers.To achieve low power dissipation,the MOS transistors in the proposed LNA are biased in moderate inversion region.It is implemented by SMIC 180 nm 1P6M CMOS process.The experiment results show that a gain of 12.14 dB@1.57 GHz is achieved with low noise figure (NF) of 1.62 dB.The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V.The ratio of gain to dc power consumption is 8 dB/mW.The size of the LNA is only 980μm× 720μm including the pads.     

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

8mW 17/24 GHz dual-band CMOS low-noise amplifier for ISM-band application

As wireless applications expand, requirements for a radio that can support multi-bands and multi-standards are continuously increasing. In a single-chip radio, a low noise amplifier (LNA) plays an important role in the noise performance or sensitivity of the total receiver chain. Although up to now a number of broadband and dualband LNAs have been reported with good performance in CMOS technology, most previous work has focused on a low frequency range, below 10 GHz. In general a dual-band LNA can be achieved by combining two LNAs in parallel for each narrow band [1]. However, this approach demands twice the power dissipation, a large chip area and therefore a significant increase in cost. Recently the low power and compact-sized dual-band LNA using a switching inductor, capacitor and concurrent method also has been reported [2?4]. In this Letter a low power concurrent dual-band LNA is proposed which is suitable for 17.1?17.3 GHz and 24?24.25 GHz industrial, scientific and medical (ISM) band application.