New insulated-gate thyristor structure with MOSFET coupled baseregions

A new insulated-gate thyristor (IGTH) structure in which the base of n-p-n transistor is coupled to the base of p-n-p transistor through a MOSFET is described for the first time, In the new structure, called base coupled insulated gate thyristor (BC-IGTH), the parasitic lateral p-n-p carrier injection inherent in previously reported thyristor structures such as the MCT, BRT, and IGTH is absent. The absence of parasitic lateral p-n-p carrier injection results in low on state voltage drop and high controllable current capability for this structure. The turn-on process in the new structure is fundamentally different from other MOS-gated thyristor structures in that in the new structure, the higher gain n-p-n transistor is turned-on first, which then provides the base drive for the lower gain p-n-p transistor. Multicellular 800 V devices of the new thyristor structure were fabricated using a double-diffused DMOS process, and were found to give on-state drop of 1.1 V at 200 A/cm², and controllable currents in excess of 100 A/cm² were obtained by forming MOS-gate controlled emitter-to-base resistive shorts     

A simple technique for improving lateral p-n-p transistor performance

Outlines a simple and elegant method that would simultaneously increase the current gain, frequency response, and voltage capability of the lateral p-n-p transistor. This is accomplished by introducing aluminium in the collector regions of the device.     

Integrated-circuit Schottky polarity guard

An aluminium Schottky-diode bridge, fabricated using a standard linear integrated-circuit process, is described. The Schottky-barrier structure effectively eliminates parasitic p-n-p transistor action, which is troublesome when collector-base diodes are used. A `guard-ring? geometry enables a reverse breakdown of 70 V to be achieved. Comparable devices made with `metal-overlap? geometry have reduced breakdowns of 36 V. A further advantage of using Schottky diodes in the bridge is their low forward drop, which for this device is 0.42 V at 10 mA. The intended area of application is in hybrid microcircuits for telephone sets.     

Analysis of n-channel MOS-controlled thyristors

The turn-off of the n-channel MOS-controlled thyristor (NMCT) is analyzed using two-dimensional simulation. A lateral NMOS-controlled thyristor structure, LNMCT, suitable for HVIC application is also proposed. It is found that the operation of a parasitic lateral n-p-n transistor in NMCT-type structures degrades the forward voltage drop and the turn-off capability and hence should be suppressed. The maximum controllable current in the NMCT is not only a function of internal parameters, but also depends on external supply voltage. This indicates that snubberless operation of an MCT-type device is not feasible. The advantages and disadvantages of the NMCT are compared with those of conventional MCT structures. The LNMCT turn-off speed is limited by the large amount of holes existing in the substrate, resulting in a turn-off waveform similar to that of an LIGBT     

A quasi-one-dimensional analysis of small-signal current gains in lateral transistors

A small-signal analysis of lateral p-n-p transistors has been made using a quasi-one-dimensional model. This model consists of a lateral p-n-p intrinsic transistor section and a vertical p-n-n⁺-p parasitic transistor section. The effect of the retarding electric field of the n⁺subdiffused layer is incorporated explicitly into the model. Besides, the field-dependent nonunity emitter efficiency of lateral transistors has also been taken into account. From the solutions of continuity equations in the base regions, closed-form expressions for small-signal current gains are obtained in terms of an ac field factor which is defined by the geometry and doping profile of the device. Frequency dependence of current gains evaluated from this analysis compares favorably with the results from an earlier two-dimensional analysis. The simplicity of the model and its reasonably good accuracy are expected to be helpful in the modeling of lateral transistors used in linear integrated circuits.     

Design techniques for IC voltage regulators without p-n-p transistors

Design techniques for IC voltage regulators without p-n-p transistors are discussed. Included is a brief discussion of the problems associated with p-n-p transistors that can be used as shunt devices in voltage regulators, as well as two methods for eliminating the p-n-p shunt device that is commonly used in regulators. The first method applies to nontemperature-compensated voltage regulators. It is a method of reducing the sensitivity of regulators to changes in power supply, using a phi cancellation technique instead of a p-n-p shunt device. This method greatly improves regulator voltage tracking. The second method is a method of eliminating the p-n-p transistor in a temperature-compensated bandgap-referenced voltage regulator using a differential amplifier to maintain current equality in tracking transistors. It is shown that the elimination of the p-n-p device will add a higher degree of design freedom while decreasing the susceptibility of the design to process variations.     

Very-low-drop voltage regulator with a fully complementary power process

A very-low-drop voltage regulator is presented that uses an isolated-collector power p-n-p transistor structure to achieve an input-output voltage drop of 0.4 V at 1 A. The device includes a circuit which prevents quiescent current peaks when the p-n-p is in saturation and a Zener-zap trimmed reference makes possible /spl plusmn/1% output voltage tolerance.     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

Gain control operation of a four-terminal p-n-p In0.53Ga0.47As/InP junction field-effect transistor grown by molecular-beam epitaxy

A four-terminal epitaxial p-n-p junction field-effect transistor grown by molecular-beam epitaxy is shown to be an effective one-component gain control element when operated as a four-terminal device. Control of amplifier gain is demonstrated by using the back-gate terminal to adjust the transconductance of a standard three-terminal transistor. The effect of parasitic capacitance on amplifier gain and cutoff frequency is described for a common-source configuration.     

A novel high performance stacked LDD RF LDMOSFET

A novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using a simple yet effective concept of stacked lightly doped drain (LDD), is proposed. The stacked layers of LDD minimizes the on-state resistance of the transistor due to the n+ doping used in the top LDD layer, and also raises the device breakdown voltage due to the charge compensation in the composite LDD region. Therefore, for the same blocking voltage rating, the stacked LDD structure allows the LDMOSFET to have a higher current handling capability. This in turn causes the transconductance Gm to be higher, leading to higher RF performance for the power device. Measured results show that a 67% improvement in I_dsat and a 16% improvement in forward blocking voltage are obtained. Furthermore, the new device achieves an increase in transconductance of 145% and improves cut-off frequency by 108% at a gate voltage of 10 V     

Vertical charge transport and charge-handling capability injunction charge-coupled devices

In junction charge-coupled devices (JCCDs), the substrate p-n-p transistor can be applied as a versatile charge-sensing element for analog outputs, in digital circuits, and as a charge-normalizing device in optical line sensors. For all these applications, operation is controlled by clock voltage waveforms and properties of the JCCD. In particular the charge-handling capability is strongly related to vertical charge flow through the substrate p-n-p. This vertical charge transport is analyzed, showing that charge-handling capability can be defined only by taking into account vertical charge flow. Several experiments that confirm the predicted behavior is given. In addition, a method to speed up the normalization of charge packets in logic applications have been performed     

Lateral complementary transistor structure for the simultaneous fabrication of functional blocks

Heretofore, the schemes for fabricating a complementary transistor structure in a monolithic functional block entailed either some additional, difficult-to-control processing steps or a sacrifice in isolation of the collector regions of one type of transistor. This paper describes an isolated p-n-p transistor structure fabricated by the same technique used for the conventional all n-p-n transistor functional block without any additional processing steps. The basic p-n-p transistor has a lateral structure. During the p-type base diffusion of the n-p-n transistor, two concentric p-type regions at close distance are selectively diffused into an isolated n- type region such as that used for the collector of an n-p-n transistor. The center p-type diffused region forms the emitter and the outer ring forms the collector. The n-type spacing between these two regions serves as the base. The current gain of this transistor is not high, typically around unity. However, by amplifying the collector current of the p-n-p transistor with an n-p-n transistor, the composite transistor acts like a high gain p-n-p transistor and the composite current gain can be made comparable to that of the n-p-n transistor in the same functional block. The lateral complementary transistor has been used extensively and successfully for the fabrication of linear functional blocks such as those used in the Advanced Minuteman Program.     

SOI横向栅控双极晶体管特性研究

横向SOI双极技术具有工艺简单、寄生电容小等优势,被认为是射频领域最有希望的技术之一。为了得到可用于射频领域的SOI横向栅控双极晶体管特性,采用一种SOI横向栅控双极晶体管器件结构,研究范围包括工艺实现过程和器件性能特性。实验表明,该器件工艺与平面CMOS工艺完全兼容,通过对栅端电压的控制,可以实现hFE在一个较大的范围内自由调节,具有更大的使用灵活性。     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

Current-gain enhancement in lateral p-n-p transistors by an optimized gap in the n+buried layer

A two-dimensional electrolytic tank analog study simulating volume recombination in the base region of lateral p-n-p transistors is presented. The effect of an n⁺buried layer is studied and it is found that a proper gap in this layer gives rise to a lateral transistor with common-emitter current-gain factor higher than that which can be achieved if the n⁺buried layer extends throughout the region below the transistor. This result is found to be true for various combinations of base geometry and minority carrier lifetimes which have been simulated. The analysis of the high-frequency performance shows that the gain-bandwidth product of the lateral p-n-p transistor is also maximized by providing an optimum gap in the buried layer.     

An analysis and the fabrication technology of the lambda bipolar transistor

A new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, which is called the Lambda bipolar transistor, is studied both experimentally and theoretically. The principal operation of the Lambda bipolar transistor is characterized by the simple circuit model and device physics. The important device properties such as the peak voltage, the peak current, the valley voltage, and the negative differential resistance, are derived in terms of the known device parameters. Comparisons between the characteristics of the fabricated devices and the theoretical model are made, which show that the analysis is in good agreement with the observed device characteristics.     

Characteristics of a p-n-p-n switch with an aluminum—Silicon Schottky diode clamp

An Al-Si Schottky diode has been incorporated in a p-n-p-n switch using a lateral p-n-p transistor and a vertical n-p-n transistor as a clamp. The switching characteristics are improved (speeded up). The dc characteristics display a negative resistance in the on region, and the on voltage at moderate currents is approximately the same as an unclamped p-n-p-n switch.     

Analysis of new high-voltage bipolar Silicon-On-Insulatortransistor with fully depleted collector

A new type of high voltage bipolar transistor for implementation in SOI material (Silicon-On-Insulator) has been developed. It is shown by measurements on fabricated structures and by numerical device simulations that the current drive capability of such a transistor is comparable to what has been achieved in a conventional transistor with buried layer and plug or in any optimized lateral transistor with buried emitter and collector layers. The new type of transistor designed in a few micrometer thick silicon layer has a breakdown voltage BV_CEO in excess of several hundreds volts and also a remarkably high Early voltage of about 400 volts. This unique Early voltage is also explained in detail by a new analytical model. The transistor is expected to have a strong impact on the feasibility to realize mixed analog and digital signal circuits with high and low voltage functions on the same chip     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage