A compact rail-to-rail output stage for CMOS operational amplifiers

This paper presents a CMOS output stage devised for driving heavy resistive loads. An operational amplifier of this type has been fabricated in a 3 μm double-polysilicon CMOS technology. With a supply voltage of ∓5 V and load of 470 Ω, the amplifier has a ∓4.6-V output swing and features a 60 mA short-circuit output current. Although simple, the proposed configuration enables the output transistors to be driven efficiently     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

Low-voltage constant-gm rail-to-rail CMOS operational amplifier input stage

This paper presents a rail-to-rail constant-g_m operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-g_m by using dummy input differential pairs. The problem which causes total g_m variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower g_m variation. The g_m of this Op Amp’s input stage varies around ±2%.     

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-μm CMOS process. Experimental results are provided and the corresponding performances are discussed and compared     

恒跨导高摆率轨对轨运算放大器的设计

本文在分析MOS管恒跨导输入级和AB类输出级运算放大器的基础上设计了一个高摆率、恒跨导的轨对轨运算放大器。在输入级中采用了齐纳二极管的稳压原理,保证Rail-to-Rail运算放大器的输入跨导恒定。为了实现高转换率,本文采用了一种新型的压摆率提高电路。另外,为了提高系统的稳定性,采用了控制零点的米勒补偿进行频率补偿。采...     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

高增益低功耗恒跨导轨到轨CMOS运放设计

基于CSMC的0.5μmCMOS工艺,设计了一个高增益、低功耗、恒跨导轨到轨CMOS运算放大器,采用最大电流选择电路作为输入级,AB类结构作为输出级。通过cadence仿真,其输入输出均能达到轨到轨,整个电路工作在3 V电源电压下,静态功耗仅为0.206 mW,驱动10pF的容性负载时,增益高达100.4 dB,单位增益带宽约为4.2MHz,相位裕度为63°。     

Push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input common-mode range

A push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input common-mode range is presented. By means of a feedback action, the circuit avoids the large magnitude deviations inherent to this type of amplifier and thus facilitates their optimisation and compensation. Simulated and experimental results obtained from a fabricated 2 mu m CMOS test chip are reported.<>     

一种改进输入级结构的轨至轨运算放大器设计

基于0.18μm CMOS标准工艺设计了一种改进输入级结构的轨至轨运算放大器电路。该电路由输入级电路、共源共栅放大电路、共源输出电路及偏置电路组成。通过引入正反馈的MOS耦合对管将输入级电路改进为预放大电路,然后对其进行了详细分析,利用Cadence软件对电路进行仿真。仿真结果表明本文结构的低频直流开环增益可以达到80 dB,比相同参数下的普通结构高20 dB左右。相位裕度达到73o,共模输入电压范围满足全幅摆动,共模抑制比低频时可以达到107 dB。     

Parallel feedforward class-AB control circuits for low-voltage bipolar rail-to-rail output stages of operational amplifiers

A new family of class-AB control circuits for bipolar rail-to-rail output stages of operational amplifiers is presented. Step by step, we report the development of five simple class-AB control circuits showing the advantages of using parallel feedforward. The circuits have been designed in such a way that temperature, supply voltage and process parameters have little influence. To test the output stages, one of them has been implemented in a very simple two-stage operational amplifier on a semi-custom chip. Measurements show a bandwidth of 2.5 MHz, a gain of 40 dB, a quiescent current of 23µA and a maximum output current of 250µA. Simulation results of three other simple operational amplifiers with the new class-AB control circuits are shown, which have a higher gain and maximum output current.     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

Constant-gm rail-to-rail CMOS op-amp input stage withoverlapped transition regions

Conventional techniques to achieve a constant-g_m rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. An economical but efficient design technique to overcome these problems is proposed. The proposed technique strategically overlaps the transition regions of the tail currents for the n- and p-pairs to achieve constant overall transconductance. Experimental results demonstrate that g_m variation can be restricted to within ±4% with improved CMRR and frequency response     

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail- to-rail input and output swing. The current headroom is 3???A and the supply voltage is 300?mV. For supply voltages down to 300?mV simulated data shows that the maximum clock frequency is approximately 600?MHz.     

A rail-to-rail input stage with constant signal behavior in 0.12 μm CMOS

This paper introduces a new fully differential low-voltage rail-to-rail input stage structure, which possesses a constant small- and large-signal behavior over the entire input common-mode range, and is suitable for low supply voltage applications in deep-submicron technologies. The proposed input stage is fabricated with two different opamp architectures in pure digital 0.12 μm CMOS technology for experimental verification. At ±0.5 V supply, the small-signal behavior variation is 5.45% across the supply rail. The large-signal behavior is constant at different input common-mode levels. The maximum current needed for the signal behavior regulation is only 90 μA.     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

A rail-to-rail input/output CMOS power amplifier

A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm² in a 3-μm technology, has a quiescent current consumption of 600 μA and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V_pp into 100 Ω (0.1% total harmonic distortion at 10 kHz)     

An input stage transconductance reduction technique for high-slew rate operational amplifiers

The use of input stage transconductance reduction as a means of decreasing monolithic op amp die size and increasing slew rate is discussed. A new input stage circuit which provides improved slew rate is presented and compared to earlier techniques.