Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Characterisation of series resistance degradation through charge pumping technique

The nature of hot carrier degradation in the spacer oxide of lightly doped drains n-MOSFETs is investigated. Damage in the spacer reveals a two-stage drain series resistance degradation with an early stage lasting about 100 ms for the technologies under consideration. Further a two-stage interface state generation separated by saturation between 1 and 10 s is observed for V_g=V_d stress condition. The co-relation between the charge pumping measurements and the drain series resistance for different stress condition is studied to investigate the nature of spacer damage. It is seen that under V_gV_t and I_submax stress conditions, the damage is predominantly by interface state generation. Under V_g=V_d stress condition the damage can be attributed to both interface state generation and trapping.     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

A new definition of threshold voltage in Tunnel FETs

This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V_TG, and one in terms of drain voltage, V_TD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on V_GS or V_DS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of V_TG and V_TD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs’ threshold voltages, as well as the dependence of V_TG on applied drain voltage and V_TD on applied gate voltage, are investigated.     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

Effect of drain voltage on channel temperature and reliability of pseudomorphic InP-based HEMTs

By performing biased accelerated life tests and three dimensional temperature simulations the effect of drain voltage on reliability and channel temperature of pseudomorphic InAlAs/InGaAs HEMTs for low noise applications was investigated. At V_d=1 V excellent long term stability in nitrogen ambient was observed. Increasing the drain voltage to V_d=2 V at constant channel temperature leads to a faster degradation rate which is caused by field accelerated degradation mechanism, probably involving fluorine diffusion. The influence of gate width on channel temperature and reliability was found to be small.     

Failure mechanisms of AlGaAs/InGaAs pseudomorphic hemt''s: Effects due to hot electrons and modulation of trapped charge

The reliability of AlGaAs/InGaAs pseudomorphic HEMT's has been investigated by means of thermal and hot-electron accelerated tests. Two commercially available devices have been tested, together with prototypes fabricated by a European supplier. Different failure modes have been observed after hot-electron testing, depending on the device type, i.e. (a) increase of drain current, I_D and threshold voltage, |V_T|, which can be attributed either to thermally-activated electron detrapping or to charge compensation by holes generated by impact ionization; (b) decrease of I_D at low drain to source voltages, V_DS, with the development of a kink in the output characteristics due to the generation of deep levels under the gate and subsequent electron trapping. In the former case, (a), hot carriers and/or high temperature storage only modulate the charge present on deep levels, leading to recoverable alterations of device characteristics. In the latter case, (b), the presence of additional deep levels under the gate leads to a permanent degradation. The link between the observed failure modes and the underlying physical mechanism is investigated by means of different techniques, and the main functional effects of the degradation modes are addressed.     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

SiC衬底上栅长70 nm fT / fmax >160 GHz的InAlN/GaN HEMTs器件

在SiC衬底上制备了InAlN/GaN 高电子迁移率晶体管（HEMTs）,并进行了表征。为提高器件性能,综合采用了多种技术,包括高电子浓度,70 nm T型栅,小的欧姆接触电阻和小源漏间距。制备的InAlN/GaN器件在栅偏压为1 V时得到的最大饱和漏电流密度为1.65 A/mm,最大峰值跨导为382 mS/mm。70 nm栅长器件的电流增益截止频率fT和最大振荡频率fmax分别为162 GHz和176 GHz。     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Bias-stress-induced increase in parasitic resistance of InP-based InAlAs/InGaAs HEMTs

The reliability of InP-based HEMTs is studied, focussing on how it is affected by the doped layer material and gate recess structure. Bias-and-temperature stress tests reveal that fluorine-induced donor passivation in the recess region, formed adjacent to the gate electrode, causes the source resistance (R_s) to increase at large drain bias voltages. The increase in R_s can be prevented by using InP or InAlP as the carrier supply layer material instead of InAlAs. On the other hand, the increase in the drain resistance (R_d) does not depend on the material of the carrier supply layer, which suggests that a mechanism different from that in the case of R_s should be considered. It is also found that a deep gate recess suppresses the increase in R_d after long-term stressing.     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Hysteresis behavior in 85-nm channel length vertical n-MOSFETsgrown by MBE

Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V_DS>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode     

Layout and bias options for maximizing Vt1 in cascoded NMOS output buffers

In this paper we investigate layout and bias options for maximizing V_t1 of the cascoded NMOSFET output buffer. Based on experimental data and device simulations we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout, and (2) how V_t1 may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.