256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate     

Optoelectronic component arrays for optical interconnection ofcircuits and subsystems

The design and performance of arrays of hybrid optoelectronic detector and modulator elements for use as optical input and output pads for chip- and board-level optical interconnects are discussed. The application of these interface arrays to specific VLSI circuits is discussed, illustrating the potential improvements in performance levels. This solder bond technique is capable of very accurate component positioning at points across the entire surface of the VLSI circuit, so that precise alignment to the optical pathways can be envisaged with optical signals taken from or delivered to any position on the chip. Measurements presented indicate that submicron positioning can be achieved. In particular, a fabrication-tolerant modulator design incorporating a chirped semiconductor mirror is reported     

A three-dimensional high-throughput architecture usingthrough-wafer optical interconnect

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications     

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

Optical Transceiver Chips Based on Co-Integration of Capacitively Coupled Proximity Interconnects and VCSELs

Combining the strengths of both proximity communication and optical communication, a new hybrid input-output (I/O) platform delivers on-chip bandwidth off-chip and over distance. We demonstrate, for the first time, a four-channel hybrid I/O interface by integrating proximity communication and vertical-cavity surface-emitting-laser-based parallel optical interconnects on the same commercial 90-nm complementary metal-oxide-semiconductor platform. The optical I/O can operate at 5 Gb/s per channel, and the complete hybrid I/O interface achieved 2.5 Gb/s per channel. We characterize the I/O link performance for various data rates and chip separations, and show 10-mum chip separation tolerance for proximity communication     

Differential detection with polymer-based etalon modulators

Differential detection of modulation from polymeric-spacer reflection etalons can provide enhanced detectability for the small modulation efficiencies of these devices. Thus, imaging arrays of modulator pairs onto arrays of detector pairs can provide highly parallel optical interconnects for very large scale integrated (VLSI) circuits. We demonstrate the effectiveness of this technique using a discrete pair of photodiodes     

System-level test and yield improvement for optoelectronic-VLSI chips

Some of the unique issues involved in testing transmitter and receiver circuits for optoelectronic-very-large-scale-integrated (OE-VLSI) applications are reviewed. In particular, the problem of testing OE-VLSI chips prior to optoelectronic device integration is outlined. Based on circuit-level approaches such as fault sensitization and novel system-level testing methodologies, the first OE-VLSI chip with testable transmitters, receivers and digital circuitry was designed in 0.35-/spl mu/m CMOS. The operation of the ASIC was verified experimentally and a fault-coverage greater than 80% is obtained, for a test time in the hundreds of microseconds range. Yield improvements ranging from 10% to 25% are predicted.     

Optically interconnected electronic chips: a tutorial and review ofthe technology

Optoelectronic interconnects between VLSI chips have been identified by the Semiconductor Industry Association (SIA) Roadmap as one of the few solutions to overcoming the communication bandwidth bottleneck between VLSI chips. Large-scale demonstrators based on optical interconnects, when fully operational, can exhibit today the same aggregate bandwidth as that foreseen by the Roadmap for the year 2007. Massive parallelism, low input/output driving energy over large distances, and synchronous processing of hundreds of optical information input channels mean that these prototypes can potentially provide on/off communication rates in the tera-pin-Hz region (i.e., a total capacity of one terabit/s). After discussing the limitations of electrical interconnects this paper reviews the means of integrating optoelectronic components with VLSI chips, suitable types of optoelectronic device and the three main approaches to constructing optical data links: fibre-ribbons, planar waveguides and free-space optics     

VLSI architectures for high-speed and flexible two-dimensionaldigital filters

Flexible VLSI architectures for high-speed 2-D finite-impulse-response (FIR) and infinite-impulse-response (IIR) digital filters are described. Cyclical parallel processing structures for 2-D FIR and IIR digital filtering are derived from the employment of storage elements. The hardware architectures that realize the parallel processing structures are developed. The resulting architectures, which are mainly constructed of three types of standard cells, exhibit a high degree of modularity and regularity, and thus a high suitability for VLSI implementation. The architectures can process 2-D data arrays of arbitrary dimensions in real time or near real time and have higher hardware efficiency and lower implementation cost than the direct-form realization     

Optoelectronic time division multiplexing

The concept of using optoelectronic (photoconductive) switches as the sampling element in time division multiplexing is introduced in the context of VLSI off-chip data transmission. A 4:1 multiplexer was fabricated in Cr : GaAs, activated by a GaAs laser via optical fibre delay lines and operated at 2.5 Gbit/s.     

Impact of three-dimensional architectures on interconnects ingigascale integration

An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9× increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits     

Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

Performance comparison between optoelectronic and VLSI multistageinterconnection networks

The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. The bases of the comparison include speed, bandwidth, power consumption, and footprint area. The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2×2 bit-serial switching elements. CMOS technology was used in the VLSI implementation, and it is assumed that the entire network resides on a single chip. Regular free-space optical interconnects are used in the optoelectronic implementation. The results show that for large networks optoelectronics offers higher speed and lower area than VLSI. Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256     

The interface processor for the Intel VLSI 432 32-bit computer

The Intel 43203 interface processor is designed to link conventional I/O subsystems and Intel's new 32-bit computer system, the iAPX432. The interface processor is an excellent example of how high density VLSI technology can be combined with innovative circuits to create highly functional systems on a single chip. This paper describes the function of the interface processor and some of the details of its implementation.     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

Progress in complementary metal-oxide-semiconductor silicon photonics and optoelectronic integrated circuits

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits(OEICs) based on a complementary metal-oxide-semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems.     

Rationale and challenges for optical interconnects to electronicchips

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects     

Optical interconnects in systems

Future enhancement of system performance will decreasingly rely on reduction in transistor dimensions. Rather, performance gains will increasingly come from improved hardware and software architectures and emerging technologies such as optical interconnects, which provide a new design space for system designers. It is possible that hybrid optoelectronic interconnects may revolutionize system implementation in the next decade     

CMOS／SEED光电子集成Crossbar互连网络的实现及控制

本文报道了光电子集成 Crossbar互连网络的光学实现及电控制方法。采用带光窗口的 CMOS/SEED灵巧像元列阵作为逻辑控制交换开关节点 ,输出光强的高低态对比度约为 1.4。由波长为 85 0 nm的半导体激光器发出的光束经过位相计算全息光栅分束器分束 ,形成 8× 2的光束阵列 ,为 CMOS/SEED光调制器窗口列阵提供泵浦光源 ,采用精密加工的高精度二维光纤阵列作为信号输入、输出接口器件。采用计算机并口产生电控制信号实现网络的交叉连接功能 ,编制了相应的控制软件。实验上完成了 16× 16 Crossbar光互连网络的交换功能