一种K波段GaAs MESFET压控振荡器的设计

利用微波晶体管的负阻特性,基于Agilent ADS软件,设计出一种K波段微带结构、变容管调谐的MESFET压控振荡器(VCO)。对VCO进行实测．结果表明,VCO的中心频率为20.56GHz,调频带宽大于100MHz,带内输出功率大于2mW,相位噪声大于-90dBc／Hz@100kHz,满足实际应用。     

一种低调谐增益变化、自适应功率控制的宽带电感电容压控振荡器

本文提出了一种电感电容宽带压控振荡器结构。为解决宽输出频率范围对振荡器调谐增益和起振条件的影响,设计了具有优化单位值的二进制开关可变电容阵列和二进制开关负阻抗阵列。该振荡器采用0.18um工艺制造,其输出频率范围约为1.9-3.1GHz。在1.8V电压下,消耗电流为14.2mA-4mA。测试结果表明,采用本文所提出调谐增益抑制技术,在整个频率调谐范围内调谐增益的变化为50-60MHz/V. 在3GHz频率处1MHz频偏下的相位噪声为-117dBc/Hz.     

一种应用于NB-IoT芯片的压控振荡器

采用40 nm 1P6M CMOS工艺,研究与设计了一款应用于窄带物联网(Narrowband Internet of Things,NB-IoT)芯片的压控振荡器(Voltage Controlled Oscillator,VCO)。该VCO利用负反馈电路降低输出的相位噪声,通过电容减敏技术降低了输出频率相对于可变电容的敏感度,通过交叉偏置二极管技术提高了VCO增益的线性度。测试结果显示:VCO所需功耗为1.2 mW;当VCO震荡在3.49 GHz时,在偏离3.49 GHz的100 kHz、150 kHz、300 kHz、500 kHz和2.5 MHz的相位噪声的测量值依次为-92 dBc/Hz、-91 dBc/Hz、-100 dBc/Hz、-110 dBc/Hz和-125 dBc/Hz;采用此压控振荡器的NB-IoT发射机输出矢量幅度误差(Error Vector Magnitude,EVM)为7.8%,频谱辐射模板(Spectrum Emission Mask,SEM)和临近信道抑制比(Adjacent Channel Power Ratio,ACPR)均满足3GPP要求。可见,测试结果证明了所提出压控振荡器电路的有效性和实用性。     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.     

增加RC压控振荡器的频率区间

典型的电压-频率转换器也叫VCO(压控振荡器),其中IC的输入电压对输出频率有一个简单的调节特性。它的一般形式为F=kV/RC,其中,RC是相关定时电阻与电容的时间常数。这些器件的输出频率范围很广,但很少有器件能够在一组     

具有电容阵列和电感阵列的1.8~2.6GHz CMOS压控振荡器

设计了一个具有开关电容阵列和开关电感阵列的1.76~2.56GHz CMOS压控振荡器。电路采用0.18µm 1P6M CMOS工艺实现。经测试,压控振荡器的频率调谐范围为37%。在频率调谐范围内及1MHz频偏处,相位噪声变化范围为-118.5dBc/Hz至 -122.8dBc/Hz。在1.8V电源电压下,功耗约为14.4mW。基于具有电容阵列和电感阵列的可重构LC谐振回路,对压控振荡器的调谐范围参数进行了分析和推导,所得结果为电路设计提供了指导。     

一种2.45 GHz低成本微带压控振荡器的设计

为了满足教学和科研的需要,基于负阻原理设计了一款工作于ISM频段2.45 GHz低成本微带压控振荡器。振荡电路采用双电源供电和共基极连接方式,利用双极性晶体管和变容二极管等分立元件制作。借助于ADS软件对电路参数及主要指标进行仿真优化,并进行了实物的加工和测试。实测结果表明,设计的压控振荡器在输入调频电压为0⁶ V时,输出振荡频率覆盖2.46 V时,输出振荡频率覆盖2.4².5 GHz,输出功率大于9.2 d Bm,相位噪声在偏离移中心频率100 k Hz处为-90 d Bc/Hz。该振荡器调谐频带线性度好,输出功率平坦度高。     

一种VHF波段CMOS压控振荡器的设计

文章设计了一款工作于VHF波段的集成LC压控振荡器.利用MENTOR公司的IC设计软件一一Eldo RF和Chartered公司的0.35μm工艺库对压控振荡器性能进行了仿真和优化,最终达到频率范围为65WHz-298MHz,最低相位噪声为-95.25789dBc@10KHz的优良性能,功耗仅为7.06mW.     

一种基于开关电容调谐的宽带压控振荡器设计

设计了一种频率可调范围约600 MHz的全集成CMOS LC宽带压控振荡器.该压控振荡器工作电压为3.3 V,基于Chartered 0.25 μm 标准CMOS工艺设计,利用开关电容调谐的方法扩大其调谐范围.测试结果表明:该压控振荡器工作在中心频率为1.9 GHz时,单边带相位噪声为-85 dBc/10 kHz,调谐范围达到32%.     

一种低噪声C类LC压控振荡器的设计

为了改善压控振荡器相位噪声,基于40 nm CMOS工艺,设计一种低噪声C类LC压控振荡器。交叉耦合NMOS对管通过电流镜偏置作为电路的电流源,并采用共模反馈偏置电路使交叉耦合PMOS对管工作在饱和区,保证LC压控振荡器实现C类振荡。通过差分可变电容的设计,压控振荡器的增益减小,压控振荡器的相位噪声得到改善。设计了4组开关电容进行调节,增大压控振荡器的调谐范围。仿真结果表明,处于1.2 V的电压下,压控振荡器振荡频率范围在4.14～5.7 GHz,频率调谐范围变化率达到31.2%,相位噪声为-112.8 dBc/Hz。     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO) with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is a...     

A BER-Based Partitioned Model for a 2.4GHz Vehicle-to-Vehicle Expressway Channel

Statistical channel models based on BER performance are presented for a frequency- and time-selective vehicle-to-vehicle wireless communications link in an expressway environment in Atlanta, Georgia, where both vehicles traveled in the same direction. The models are developed from measurements taken using the direct sequence spread spectrum (DSSS) technique at 2.45GHz. A collection of tapped delay line models, referred to as a “partitioned” model in the paper, is developed to attempt to capture the extremes of BER performance of the recorded channel. Overall and partition models are compared to the recorded channel in terms of the BER statistics obtained when the channels are inserted in a dedicated short range radio (DSRC) standard simulation system. The quality of the match between synthesized and recorded channel BER statistics is analyzed with respect to type of modulation (fixed or adaptive), the frame length, and the length of the interval over which the BER was calculated. Guillermo Acosta was born in Mexico City, Mexico, in 1962. He is a Ph.D. Candidate and a graduate research assistant in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, in Atlanta, Georgia. He obtained his Bachelor of Engineering with Honors and Master of Engineering, both in Electrical Engineering, from Stevens Institute of Technology, Hoboken, New Jersey, in 1985 and 1987, respectively. He also obtained a Master of Business Administration with Honors from the Instituto Tecnologico Autonomo de Mexico (ITAM), Mexico City, Mexico, in 1996. Mr. Acosta has held technical and managerial positions in the recording, radio, and TV industries and in the Communications Ministry of Mexico. He has been an adjunct instructor in Electrical Engineering in the Instituto Tecnologico y Estudios Superiores de Monterrey Campus Estado de Mexico (ITESM-CEM) and the Universidad Iberoamericana. He is member of the IEEE, INCE, Tau Beta Pi, and Eta Kappa Nu. Mary Ann Ingram received the B.E.E. and Ph.D. degrees from the Georgia Institute of Technology, in Atlanta, Georgia, in 1983 and 1989, respectively. From 1983 to 1986, she was a Research Engineer with the Georgia Tech Research Institute in Atlanta, performing studies on radar electronic countermeasure (ECM) systems. In 1986, she became a graduate research assistant with the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where in 1989, she became a Faculty Member and is currently Professor. Her early research areas were optical communications and radar systems. In 1997, she established the Smart Antenna Research Laboratory (SARL), which emphasizes the application of multiple antennas to wireless communication systems. The SARL performs system analysis and design, channel measurement, and prototyping, relating to a wide range of wireless applications, including wireless local area network (WLAN) and satellite communications, with focus on the lower layers of communication networks. Dr. Ingram is a Senior Member of the IEEE.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 6-7 GHz, 40 dB receiver RF front-end with 4.5 dB minimum noise figure in 0.13μm CMOS for IR-UWB applications

A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP₃ of-11 dBm.The core receiver （without test buffer） consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm² area.     

A new closed form method for design of variable bandwidth linear phase FIR filter using Bernstein multiwavelets

In this paper, a new method for the design of variable bandwidth linear-phase finite impulse response filters using Bernstein polynomial Multiwavelets is proposed. In this method, approximation has been achieved by linearly combining the fixed coefficient linear phase filters with Bernstein multiwavelets, which are used to tune bandwidth of the filter. Optimisation has been achieved by minimising the mean square error between the desired and actual filter response which leads to a system of linear equations. The matrix elements can be expressed in form of Toeplitz-plus-Hankel matrix, which reduces the computational complexity. The simulation results illustrate significant improvement in errors in passband (e_p), and stopband (e_s) as compared to earlier published work.     

Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.