Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.     

Core-unified soc test data compression and application

The pattern run-length coding test data compression approach is extended by introducing don’t care bit (x) propagation strategy into it. More than one core test sets for testing core-based System-on-Chip (SoC) are unified into a single one, which is compressed by the extended coding technique. A reconfigurable scan test application mechanism is presented, in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added. The proposed union test technique is applied to an academic SoC embedded by six large ISCAS’89 benchmarks, and to an ITC’ 02 benchmark circuit. Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve test data compression/decompression, but also reduce the redundant shift and capture cycles during scan testing, de-creasing SoC test application time effectively.     

Domain Coverage Metric for SoC Validation

The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.     

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.     

Application of Rollout Strategy to Test Points Selection for Integer-Coded Fault Wise Table

Test points selection for integer-coded fault wise table is a discrete optimization problem. The global minimum set of test points can only be guaranteed by an exhaustive search which is eompurationally expensive. In this paper, this problem is formulated as a heuristic depth-first graph search problem at first. The graph node expanding method and rules are given. Then, rollout strategies are applied, which can be combined with the heuristic graph search algorithms, in a computationally more efficient manner than the optimal strategies, to obtain solutions superior to those using the greedy heuristic algorithms. The proposed rollout-based test points selection algorithm is illustrated and tested using an analog circuit and a set of simulated integer-coded fault wise tables. Computa- tional results are shown, which suggest that the rollout strategy policies are significantly better than other strategies.     

Circuit testable design and universal test sets for multiple-valued logic functions

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n＋1 vectors detect all skew faults in the circuit realization of multiplevalued functions with n inputs. Secondly, min（max） bridging fault test sets with n＋2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiplevalued logic functions.     

Event-Based Reliable H∞ Control for Networked Control System with Probabilistic Actuator Faults

This paper investigates the reliable con- troller design for networked control system with proba- bilistic actuator faults under event-triggered scheme. The key idea is that only the newly states violating specified triggering condition will be transmitted to the controller. Considering the effect of the network transmission delay, event-triggered scheme and probabUistic actuator faults with different failure rates, a new actuator fault model is proposed. Criteria for the exponential stability and criteria for co-designing both the feedback and the trigger param- eters are derived by using Lyapunov functional. These cri- teria are obtained in the form of linear matrix inequalities. A simulation example is employed to show the effectiveness of the proposed method.     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.     

Fault detection for multiple-valued logic circuits with fanout-free

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m > 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n + 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in th     

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved.     

Test Challenges in Nanometer Technologies

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.     

基于扫描的SoC全速测试及应用

介绍了在系统级芯片(SoC)测试中所用到的基于扫描结构的全速测试。首先介绍了转换故障模型和路径延迟故障模型,以及测试时采用的具体的两种测试方法,然后总结了一些测试时要注意的事项。最后结合上述理论,对一款基于ARM的自主研发SoC芯片进行了实验,并用时序测试矢量对stuck-at故障进行模拟,减少了测试矢量的个数,节约了测试成本,得到了预期的结果。     

A High-Speed Pseudorandom Test Pattern Generator

Real-time built-in self-testing (BIST) of digital devices that incorporate functional modules of various speed is considered. A method of designing a pattern generator is suggested. This generator is capable of forming pseudorandom test patterns both with the normal speed (one test vector per clock cycle) and with a speed several times higher (several test vectors per clock cycle). With these generators, at-speed testing of multichip module components can be performed to detect both stuck-at and ac faults.     

基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

Constructing IP cores’ transparency paths for SoC test access using greedy search

Today’s SoC design demands efficient test access mechanism to develop and perform manufacturing test. Transparency based methods have their advantages for IP cores’ test reuse in SoC level. In this paper, an IP core transparency paths construction approach employing greedy search strategy based on gate-level heuristic information is proposed. With these transparency paths, IP cores can consecutively transfer one test per clock cycle from their inputs to outputs, and thus can be used in transparency-based test scheme to benefit at-speed testing and decrease the demand of parallel TAMs. The experimental results show lower extra overhead needed in our approach than conventional boundary scan and previous RT level approaches.     

Functional fault models for non-scan sequential circuits

The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.