倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

倒装焊封装中无铅焊点在封装工艺中的热机械力学分析

采用粘塑性Garofalo—Arrhenius模型描述无铅焊料的蠕变行为，确定了96．5Sn3.5Ag焊点材料的模型参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元法模拟了无铅板上倒装焊在封装工艺及热循环条件下的应力应变行为。结果表明由于无铅技术在封装中的引入，封装工艺对倒装焊器件的影响更为重要。     

剪切蠕变下无铅焊点厚度的尺寸效应

利用自制的电子测试系统,测量分析了试样焊点厚度(0.05～0.50mm)对电阻应变的影响。结果表明:在剪切蠕变条件下,焊点厚度为0.25mm时,电阻应变最小,蠕变寿命最长。利用有限元软件ANSYS对焊点的蠕变应变进行仿真分析。结果显示:随着焊点厚度变化,焊点蠕变应变的变化趋势与实验结果一致。将相同厚度下的电阻应变与蠕变应变进行拟合,得到了电阻应变与蠕变应变之间的定量关系式。     

湿热载荷对含底充胶的FCOB器件界面分层影响

分析了湿气在FCOB器件中的扩散行为,然后分别对湿热集成载荷和热载荷作用下的FCOB器件进行了有限元仿真研究。结果表明,硅芯片与底充胶界面拐角处吸湿最多,应力集中最为严重;吸潮后,低温保温结束时刻,该处同时湿热载荷影响,比单纯热载荷影响下,等效Von Mises应力和等效总应变分别增大了58%和60%,说明该处是底充胶分层萌生的潜在位置。     

电迁移致无铅钎料微互连焊点的 脆性蠕变断裂行为

研究了电迁移条件下不同电流密度(0.8~1.27×10⁴A/cm²)和通电时间(0~96 h)对无铅钎料模拟微互连焊点的蠕变断裂行为的影响.研究结果发现,电迁移作用加速了焊点的蠕变断裂过程,随着电迁移通电时间的延长及电流密度的增加,其蠕变应变速率显著增大,而蠕变寿命逐渐缩短;电迁移还导致焊点蠕变断裂机制发生明显变化,在高电流密度或长时间通电的电迁移后,微互连焊点在服役条件下会发生由延性断裂向脆性断裂的转变.     

基于电阻应变的无铅焊点损伤临界点在线检测

蠕变损伤是引起焊点失效的重要因素,实验表明在蠕变过程中存在一个临界点,在临界点之前蠕变呈现一种缓慢的增长趋势,而在临界点之后蠕变加速进行,导致焊点很快失效。找出此临界点对了解焊点的性能及寿命预测有重要意义,但传统的蠕变测试方法不能实时测得焊点的蠕变损伤临界点。研究表明焊点的蠕变损伤与其电阻变化存在着线性关系,因此可以通过测量焊点的电阻变化来监测其蠕变情况。文章以单个无铅焊点为研究对象,利用特制的无铅焊点微电阻在线测量系统,实时监测焊点在蠕变过程中的电阻变化,并利用二次移动平均法建立焊点电阻的预测模型,通过对比预测电阻值与实测值的差异实时找出焊点的损伤临界点,为蠕变测试研究提供了一种新的方法。     

CSP封装Sn-3.5Ag焊点的热疲劳寿命预测

对芯片尺寸封装(CSP)中Sn-3.5Ag无铅焊点在热循环加速载荷下的热疲劳寿命进行了预测.首先利用ANSYS软件建立CSP封装的三维有限元对称模型,运用Anand本构模型描述Sn-3.5Ag无铅焊点的粘塑性材料特性;通过有限元模拟的方法分析了封装结构在热循环载荷下的变形及焊点的应力应变行为,并结合Darveaux疲劳寿命模型预测了无铅焊点的热疲劳寿命.     

CSP封装Sn-3.5Ag焊点的热疲劳寿命预测

对芯片尺寸封装(CSP)中Sn-3.5Ag无铅焊点在热循环加速载荷下的热疲劳寿命进行了预测.首先利用ANSYS软件建立CSP封装的三维有限元对称模型,运用Anand本构模型描述Sn-3.5Ag无铅焊点的粘塑性材料特性;通过有限元模拟的方法分析了封装结构在热循环载荷下的变形及焊点的应力应变行为,并结合Darveaux疲劳寿命模型预测了无铅焊点的热疲劳寿命.     

BGA焊点在板级跌落实验中的疲劳寿命估计

按照JEDEC标准对板级跌落实验的要求测试了有铅和无铅焊点的球栅阵列封装.用ANSYS软件建立了有限元分析模型,并用ANSYS/LS-DYNA直接求解器计算了典型结点的应力和应变,以及每次跌落时积累在焊点中的平均应变能密度.利用实验和模拟的结果重新计算了Darveaux模型中的常数,将这个模型的应用范围扩展到了跌落环境,并计算了各种条件下焊点的疲劳寿命.     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

Investigation on flip chip solder joint fatigue with cure-dependent underfill properties

A cure-dependent viscoelastic constitutive relation is applied to describe the curing process of epoxy underfill in flip chip on board (FCOB). The chemical shrinkage of the epoxy underfill during the curing process is applied via incremental initial strains. Thus, the stress and strain build-up, caused by the simultaneous increase in stiffness and shrinkage during the curing process, are simulated. Accelerated fatigue experiments with thermal cycles from -55/spl deg/C to 80/spl deg/C are carried out for a specially designed flip chip configuration. Based on the obtained curing induced initial stress and strain fields, thermo-mechanical predictions are presented for the test carriers. The solder bumps are modeled with temperature dependent visco-plastic properties. A combination of a Coffin-Manson based fatigue relation and a creep fatigue model is used as fatigue failure criterion. The results show that the finite element method (FEM)-based fatigue life predictions match better with the experimental results, if the curing induced initial stress state is taken into account. The effect of cure-induced hydrostatic stress is qualitatively investigated by using a modified energy partitioning damage model with a correction factor in the creep damage formulation to take into account the effect of the hydrostatic stress.     

Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages

This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modelling. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the effect of thermal cycling conditions has been investigated. Comparing the induced inelastic strains in the solder joint, the lead-free SnAgCu generally scores better thanks to the lower creep strain rate. On the other hand for the CSP and flip chip package, SnAgCu scores worse for the more extreme loading conditions when the inelastic dissipated energy density is selected as damage parameter. The main reason is that due to the lower creep strain rate, the stresses become higher for SnAgCu resulting in higher hysteresis loops with more dissipated energy per cycle. For the QFN package, SnAgCu scores much better.     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Moisture-induced failures of adhesive flip chip interconnects

Adhesive flip chip interconnect has been recognized as a promising substitute for solder interconnection due to its fine-pitch, lead-free, and low-temperature processing capabilities. As adhesives are made of polymers, moisture absorption by the polymeric resin remains as one of the principal contributors to adhesive joint failure mechanisms. In this research, the reliability performance of the adhesive flip chip in the pressure cooker test and moisture sensitivity test conditions was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different sizes of bump/pad opening in the interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between adhesive and other components in the package, which induces a hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated from the standpoint of finite element modeling. In this study, it is concluded that hygroscopic swelling assisted by loss of adhesion strength upon moisture absorption is responsible for the moisture-induced failures in these adhesive flip chip interconnects.     

Effects of underfill material properties on the reliability ofsolder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput