Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

A physical model for the gate current injection in p-channelMOSFET's

A quantitative physical model for calculating the hot-electron injection probability, I_G/I_SUB, for both buried and surface p-channel MOSFETs is presented. The model utilizes the two-dimensional potential contours generated by PISCES, and integrates the probability of substrate hot-electron injection across the high-field region near the drain. The known phenomenon that buried-channel (BC) PMOS has higher hot-electron injection probability but lower channel field (I_SUB/I_D) than a similar surface-channel (SC) device is successfully modeled. This phenomenon can be attributed to the larger energy band hump-up near the drain and the larger oxide field (and thus greater barrier lowering) at a given bias condition for the buried-channel device. The I_G characteristics can be obtained from the calculated I_G /I_SUB ratio, using readily available I_SUB values     

A novel method for extracting the metallurgical channel length ofMOSFETs using a single device

A new charge-pumping method with dc source/drain biases and specified gate waveforms is proposed to extract the metallurgical channel length of MOSFETs by using a single device. Using two charge-pumping currents of a single nMOSFET measured under different V _GL (V_GH for pMOSFETs), the metallurgical channel length can be easily extracted with an accuracy of 0.02 μm. It is shown that the proposed novel method is self-consistent with the results obtained by the charge-pumping current measured from multidevices under different gate pulse waveforms and bias conditions     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

A model for hot-electron-induced MOSFET linear-current degradationbased on mobility reduction due to interface-state generation

A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E_eff. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L_eff=0.2-1.5 μm and T_ox=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient α, which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E_eff determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L_eff and T _ox     

Ensemble Monte Carlo study of interface-state generation inlow-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFETs. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-μm channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.44 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO₂ interface). These simulations demonstrate that “lucky electron” and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-μm channel lengths     

Reduction of channel hot-electron-generated substrate current insub-150-nm channel length Si MOSFET's

Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 μm, and a family of characteristic plots of substrate current, normalized to drain current, I_SUB/I_D, rather than (V _DS-V_DSAT)^-1 was obtained. For channel lengths greater than 0.5 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the normalized substrate current at constant V_DS increases with decreasing channel length. However, as the channel length is decreased below 0.15 μm, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both     

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed     

Scaling properties and short-channel effects in submicrometerAlGaAs/GaAs MODFET's: A Monte Carlo study

Scaling properties of n⁺-Al_xGa_1-xAs/GaAs MODFETs with submicrometer gate lengths (L_G=0.50 to 0.05 μm) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be ≈0.10 μm. Devices with smaller gate lengths than 0.1 μm exhibit degraded transconductance (g_m), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (R_o). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from g_m and f_t measurements are reconciled     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Simplified Z-propagating DC bias stable TE-TM modeconvertor fabricated in Y-cut lithium niobate

A TE-TM mode converter, useful at either 0.632 or 0.840 μm, has been fabricated on y-cut LiNbO₃ by Ti indiffusion with the channel waveguide placed parallel to the z-axis. For TE polarized input, the maximum TM modulation depth is 97 percent at 0.632 μm with a 5-V (pp) drive and 99 percent at 0.840 μm with a 12-V (pp) drive. A similar device operating at 1.3 μm displays 98-percent TE-TM switching at 68 V. Operation involves only coplanar electrodes placed alongside the channel acting on the r₆₁ electrooptic coefficient. A separately deposited buffer layer is unnecessary. Testing indicates a substantially greater tolerance to electrode misalignment than afforded by similar structures formed in x-cut substrates. Data illustrating immunity to photorefractive drift in the presence of a DC bias voltage is presented for 0.840-μm wavelength operation     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

Dependence of ionization current on gate bias in GaAs MESFETs

The nonmonotonic behavior of gate current I_g as a function of gate-to-source voltage V_gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I_g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I_g(V_gs) curve is strongly related to the drop of the electric field in the channel of the device as V_gs is moved towards positive values     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

A self-aligned gate lightly doped drain (Al, Ga)As/GaAs MODFET

An asymmetrical lightly doped drain (LDD) (Al, Ga)As/GaAs modulation-doped FET (MODFET) structure with high drain-to-source and drain-to-gate breakdown voltages was fabricated. The LDD structure has a self-aligned lightly doped n^- region between the channel and a heavily doped n⁺ region at the drain, to reduce the electric field and impact ionization. The length of the lightly doped n ^- region on the drain side was varied from 0 to 1 μm. Drain-to-source breakdown voltage BV_ds improved from 4.6 to >10 V while the transconductance g_m remained unchanged. The drain-to-gate reverse breakdown voltage BV _dg increased from ≈7 to >20 V. The two breakdown mechanisms are believed to be independent. The LDD MODFET should find widespread application in circuits requiring high breakdown voltage such as high-speed analog-to-digital converters (ADCs) and microwave power amplifiers     

Unified characterization of two-region gate bias stress insubmicrometer p-channel MOSFETs

P-channel MOSFETs stressed at a given drain voltage over the entire range of device saturation, 0 V⩽|V_G|⩽|V_D |, are discussed. Two different gate currents of opposite polarity were observed. These gate currents are shown to be correlated with device degradation behavior, which is distinctly different in each case. The gate bias thus divides into two stress regions, corresponding to small and large |V_G|. In the former, the parameter shift is initially pronounced but saturates in time. In the latter, the device degradation is initially small but cumulative in time. Therefore, both stress regions are equally important in affecting the device lifetime. A phenomenological model of gate current to support the two-region gate stress model is presented     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.