Design and optimization of vertical SiGe thyristors for on-chip ESD protection

We present extensive measurement results investigating the design and optimization of vertical SiGe thyristors for use as ESD protection elements in RF integrated circuits. Experiments include variations of the anode material, contact geometry, and buried layer, as well as a detailed study of optimal area scaling. RF characterization using S-parameter data is presented.     

A modified LDMOS device with improved ESD protection performance

A modified lateral‐diffusion metal–oxide–semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high‐voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon‐controlled rectifier (LDMOS‐SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS‐SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.     

基于嵌入式技术的微机保护装置

基于IEC60870-5-104规约,利用嵌入式ARM(Advanced RISC Machines)处理器强大的以太网通信功能和数字信号处理器DSP(Digital Signal Processor)实现微机距离保护功能。分析了ARM和DSP结构及双口RAM用于双处理器间的高速数据交换的特点。构造了距离保护的判据和算法。保护算法在Matlab仿真和试验中都验证了保护装置的可靠性、速动性、选择性、灵敏性。     

基于嵌入式技术的微机保护装置

基于IEC60870-5-104规约,利用嵌入式ARM(Advanced RISC Machines)处理器强大的以太网通信功能和数字信号处理器DSP(Digital Signal Processor)实现微机距离保护功能.分析了ARM和DSP结构及双口RAM用于双处理器间的高速数据交换的特点.构造了距离保护的判据和算法.保护算法在Matlab仿真和试验中都验证了保护装置的可靠性、速动性、选择性、灵敏性.     

静电防护测量仪器综述

静电防护测量仪器是依据静电防护标准中的技术指标要求设计的.本文分析了静电防护被测对象的技术要求和特点,以及它们所依据的技术标准,总结归纳了静电防护领域常用的测量仪器,按照被测参量分为:电阻、静电电压、静电电荷量以及静电放电屏蔽等测量仪器,列举了典型仪器的测量原理、特点,以及各类仪器的发展趋势.     

带智能报警仪的脚腕带的开发与研究

本文主要阐述了一种带智能报警仪的脚腕带的设计,使防静电脚腕带的适用范围更广,并实现实时监控脚腕带的静电导通情况,使防静电脚腕带的使用更加智能化、防呆化,提高生产车间防静电的效果。     

Accurate wafer-level measurement of ESD protection device turn-onusing a modified very fast transmission-line pulse system

Quantifying the turn-on behavior of electrostatic discharge (ESD) protection devices under subnanosecond transients is critical to achieving robust protection against the Charged Device Model stress. A wafer-level very fast transmission-line pulse system (VFTLP) has been developed and is shown to successfully measure the turn-on time of a common ESD protection device. Both formal analysis and practical details regarding VFTLP system construction and operation are documented     

Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology     

The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology

The dependences of drift implant and layout parameters on electrostatic discharge (ESD) robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better transmission line pulsing (TLP)-measured secondary breakdown current (It2) and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon-controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and human-body-model ESD levels on the spacing from the drain diffusion to polygate are different.     

Novel on-chip fully monolithic integration of GaAs devices with completely fabricated Si CMOS circuits

We monolithically integrated polycrystalline GaAs metal-semiconductor-metal (MSM) photoconductive switches with a completely fabricated Si-CMOS amplifier and obtained a properly functional optical receiver, without altering the Si circuit performance. To our knowledge, this is the first time a fully monolithic on-chip integration has been achieved.     

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that this impact of gate bias depends on the finger width of the protection devices. In addition, it has been established that substrate biasing can effectively alleviate the adverse impact of the gate bias and can improve ESD strength despite the gate-coupling level. Improved understanding of ESD behavior for advanced devices under high gate-coupling conditions can extend design capabilities of protection structures.     

电子式电能表静电放电试验及防护措施

介绍了静电放电(ESD)的机理,提出了基于国家标准GB/T 17215.211-2006和 GB/T 17626.2-2006 的试验配置、试验方法和结果评估,给出了有效的静电放电防护措施.     

ESD protection for SOI technology using under-the-BOX (substrate) diode structure

This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SOI wafer, without additional steps to the conventional SOI CMOS process. This paper shows that the ESD protection level can reach four times the level of the standard SOI lateral-diode structure. This paper presents the device and process simulation results to demonstrate the effect of self-heating in both the standard SOI lateral and substrate diodes, and to demonstrate how to optimize the SUBD structure using a deep n-well implant.     

一种母线综合后备保护装置

针对110 k V环网运行方式,分析了传统保护配置方案存在的问题,并提出了一种母线综合后备保护装置。利用主变远后备保护动作跳母联的信号,提出了全新的110 k V线路综合后备保护,并将其与断路器失灵保护集成于一体,形成了完整的解决方案。该装置能够有效防止110 k V线路发生故障时因单重化线路保护装置拒动或者断路器失灵导致主变后备保护无选择性越级跳本侧断路器的问题,缩小停电范围,提高供电可靠性。仿真和试验结果表明了理论分析的正确性以及策略的有效性。     

Programmable protective device for LVdistribution system protection

High quality electric power supply is the prime goal in the modern power systems around the world. One of the main ways to achieve this is the protection of the system which needs to be fast, reliable and cost effective. The objective of this paper is to provide protection of equipments in low voltage (LV) distribution system and thereafter to avoid their failure due to abnormal operating conditions. The proposed device provides protection for industrial, commercial and residential equipments by monitoring under voltage, over voltage and over current conditions using microcontroller, transistor and other discrete components. The microcontroller is the heart of this protective device which performs the major control of the device. The designed circuit can withstand the loads and the set voltage range so as to supply the connected load for any voltage variation between 220 and 240 Volts. It can be used to protect loads such as refrigerator, TV, VCR/DVD player etc. against undesirable over and under voltage conditions as well as surges caused due to sudden failure of power supply mains. This device can also be used directly as standalone equipment between the supply mains and the load. The over/under voltage and over current cut-off with time delay provides over/under-voltage and over current protection and also protection against any transients.     

基于集成短引线保护功能的输电线路保护装置设计

变电站在建设中经常会遇到部分线路建设滞后无法与厂站同时投运的情况,对于3/2接线方式的变电站会造成相关间隔断路器无法成串运行,导致电网运行安全性降低。通过介绍在现场采取的三种解决方案及存在问题,提出开发一种集成短引线的线路保护装置及适用于 3/2接线方式的短引线和输电线路运行状态识别方法,通过专业仿真和动模实验验证了该方法的正确性及可靠性。     

大型变压器微机保护装置研制

结合大型变压器微机保护的开发实践,对保护系统的硬件设计、不同保护原理的综合应用以及保护软件的编程实现方法等方面进行了研究和探讨。所开发的保护装置集主、后备保护于一体,通过采用高性能的TMS320C6713DSP作为保护CPU和配备带有嵌入式Linux操作系统的ARM处理器作为管理机,满足了复杂保护的应用要求。主保护通过综合采用多种保护原理,充分发挥不同保护原理的优势,进一步提高保护的综合性能。同时,借助功能强大的硬件平台,在软件设计中采用基于"继电器"功能模块的设计方法,实现了程序的模块化和透明化,提高了软件开发效率,且易于维护和扩展功能。目前,该装置已通过静模测试和动模实验。     

继电保护装置运行年限评价的研究

针对继电保护状态检修中一刀切地评价装置运行年限的问题,介绍了一种装置合理运行年限估计的方法。首先以装置缺陷产生原因和失效率特点将装置缺陷分为早期缺陷、偶热缺陷和老化缺陷。然后将装置现场数据作为随机截尾试验数据分类计算装置中后期缺陷发生次数期望,其中早期缺陷为固定值,偶然和老化缺陷分别符合指数和威布尔分布。接着分析状态检修制度和装置配置方式对检修工作开展的影响,从而构建以单位时间费用最小为目标的函数估计装置合理的运行年限。最后利用某地区线路保护装置现场数据说明本方法的可行性。     

保护继电器综合测试仪的研制

给出了一种多功能保护测试仪的原理、电路结构及测试方法。