An improved MOSFET model for circuit simulation

Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

SPICE source code implementation of aDC model for the non pinchoff depletion mode MOSFET

The implementation of the Lin model for the non pinchoff depletion mode MOSFETs directly into the source code of the SPICE 2G.5 circuit simulation program is described. The computational advantages of our implementation over Lin's subcircuit approach are pointed out, and, more significantly, certain previously undiscovered limitations of both methods are discussed. The encoding of the model into SPICE is described in sufficient detail so as to be duplicable by other interested researchers. Our results compare favorably to experiment and to the more comprehensive El-Mansy model. Finally, a new method of parameter extraction is described for the El-Mansy model, which makes it possible to derive the parameters of the Lin and El-Mansy models simultaneously.     

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain–frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.     

An improved analysis for the nonlinear performance of body-driven analog MOSFET circuits

This article discusses the nonlinear performance of body-driven analog long-channel MOSFET circuits. Analytical expressions are obtained for the nonlinear distortion products resulting from sinusoidal excitation of the body terminals. The special case of a single sinusoid excitation is considered in detail, and conditions for harmonic suppression are obtained.     

Unified 1/f noise SOI MOSFET modelling for circuit simulation

The authors address the modelling of 1/f noise in SOI MOS devices for circuit simulation. A simple and unified model is presented which is valid for all operating regimes; it is verified by comparison with noise measurements. It is shown that this model is especially useful for low-power SOI MOS circuit design     

MOSFET modeling for analog circuit CAD: problems and prospects

The requirements for good MOSFET modeling are discussed, as they apply to usage in analog and mixed analog-digital design. A set of benchmark tests that can be easily performed by the reader are given, and it is argued that most CAD models today cannot pass all the tests, even for simple, long-channel devices at room temperature. A number of other problems are discussed, and in certain cases specific cures are suggested. The issue of parameter extraction is addressed. Finally, the context of model development and usage is considered, and it is argued that some of the factors responsible for the problems encountered in the modeling effort are of a nontechnical nature     

Interdigital piezoelectric Rayleighwave transducer: an improved equivalent circuit

A more accurate representation of an interdigital array is obtained by using an equivalent circuit intermediate between the crossed-field and in-line-field models, with negative capacitance, velocity, length and coupling dependent on the electrode-width/gap-between-electrodes ratio.     

Low voltage high performance E/D MOS logic

The letter describes a high performance MOS technology which produces both enhancement- and depletion-mode devices on the same substrate without using ion implantation. The enhancement mode devices, with 1?2 ?m channel lengths, can be realised using regular optical lithography and simple processing techniques.     

Dynamic segmentation of cellular networks for improved handover performance

One of the most important initial steps, inherent in the planning procedure of cellular networks, is their segmentation in operational parts that is performed at different levels corresponding to the hierarchy and topology of the network. The major goal of this procedure is the efficient deployment of the system and management of the distributed segmented parts while minimizing the signaling overhead in the network. As we show here, it can take place even during the operational phase of the network when certain shortcomings appear. In this work, we present an approach based on graph theory for the segmentation of cellular networks at the Base Station Controller (BSC) level that achieves a significant increase in the performance of the network. In particular, with the proposed method, both the handover attempts when a mobile station is moving to a cell belonging to a different BSC as well as the corresponding handover failure rate are decreased significantly, allowing for a continuous network upgrade. Copyright © 2007 John Wiley & Sons, Ltd.     

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (I_ds) and other for cut-off frequency (f_T) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65 V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of I_on/I_off, Subthreshold Swing (SS), device efficiency, f_T, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.     

Analysis and modeling of an improved dual-array D/A network for SAR A/D converter

Based on the discussion of traditional dual-array charge scaling D/A conversion approach, an improved D/A network for successive approximation A/D converter (ADC) is proposed in this letter. With a unit capacitor instead of traditional non-integral scaling capacitor and by adding several additional logic control signals, this novel D/A network is easier to realize in process than traditional dual-array approach. Theoretical analysis and high-level Matlab modeling results prove that this improved D/A network is suitable for embedded SoC applications.     

An improved input protection circuit for C-MOS/SOS arrays

A protective network for silicon-gate C-MOS/SOS arrays has been designed that is capable of protecting input circuits from static discharges in excess of 2200 V. This paper describes the results of a program undertaken at RCA to develop a protection network for C-MOS arrays on sapphire substrates capable of withstanding 1500-v static discharges. A test chip with eight input protection configurations was designed, processed, and tested. The results were incorporated into a network design that exceeds the requirements without degrading circuit speed.     

改进的二维三维混合时域不连续伽辽金方法

对高速信号通过电源板时的电源完整性(power integrity, PI)问题进行研究时, 因为电源板中主要模式分布为零阶平行板模式, 可以采用二维简化以提高效率.而对于隔离盘或其它存在纵向不连续性的区域, 则应采用三维算法以保证精度.将两者结合起来的一种二维三维(2D/3D)混合时域不连续伽辽金(discontinuous Galerkin time domain, DGTD)方法可以兼顾精度与效率, 有效地处理这类电磁全波计算问题.其中二维、三维方法采用同一套三棱柱离散的网格, 通过适当设置基函数, 二维区域与二维区域之间可以方便快速地相互转化.随着电磁波的传播, 二维、三维的适用区域是随时间、空间动态变化的.为了准确地捕捉这种动态变化, 文中提出的一种改进的自适应判据, 在每个时间歩对电磁场进行检测, 从而动态地判定二维简化区域.与现有技术的判据控制绝对误差不同, 该方法对相对误差进行控制, 效率高、精度好, 对于不同的结构适应性强.通过数值实验, 与商业软件和全三维(3D)DGTD方法的结果进行了比较和验证.     

半导体激光器改进电路模型的大信号验证

实现了一种可以对于反射系数进行精确建模的半导体激光器电路模型并且与传统模型进行了比较。在ADS(Advanced Design Systems)中使用了SDD(Symbolic Defined Devices)器件实现,对于速率方程进行了变形以改进模型的收敛性,该模型可用于大信号仿真。对于不同偏置条件下的半导体激光器的反射系数进行了仿真并且和测量结果进行了对比。首次在大信号仿真中验证了改进模型的精确性。     

Improved small-signal equivalent circuit model and large-signalstate equations for the MOSFET/MODFET wave equation

A simple non-quasi-static small-signal equivalent circuit model is derived for the ideal MOSFET wave equation under the gradual channel approximation. This equivalent circuit represents each Y-parameter by its DC small-signal value shunted by a (trans) capacitor in series with a charging (trans) resistor. A large-signal model for the intrinsic MOSFET is derived by first implementing this RC topology in the time domain. Modified state equations are then introduced to enforce charge conservation. Transient simulations with this approximate large-signal model yield results that are compared with reported exact numerical analysis for the long channel MOSFET for a wide range of bias conditions. This unified small- and large-signal model applies to both the three- and four-terminal intrinsic MOSFET in the region of the channel where the gradual channel approximation is applicable. A non-quasi-static small-signal equivalent circuit for the velocity-saturated MOSFET wave equation is also reported     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.