制备工艺对0.7CaTiO3-0.3NdAlO3材料的影响

用固相反应和熔盐法制备工艺合成了0.7CaTiO3-0.3NdAlO3(CTNA)粉体,研究了制备工艺对CT-NA陶瓷的合成过程和微波介电性能的影响。结果表明,相比于固相反应的长时间合成,熔盐法中,混合粉料在1 200℃2、h下即可合成CTNA单相,样品在1 375℃下可烧结致密,获得的样品具有与固相反应相当的微波介电性能,即介电常数rε=43;品质因数与频率的乘积Q×f=35 736 GHz;频率温度系数τf=1.32×10-6/℃。     

CaWO_4-Li_2WO_4陶瓷低温烧结特性及微波性能研究

采用固相反应法制备了(1-x)CaWO4-xLi2WO4(0≤x≤0.14)微波陶瓷,研究了Li2WO4作为第二相对CaWO4微波陶瓷的低温烧结特性和微波性能的影响。结果表明,Li2WO4相的存在能明显降低CaWO4的烧结温度,并且随着x的增加,(1-x)CaWO4-xLi2WO4(0≤x≤0.14)陶瓷体系的最佳烧结温度降低。当x=0.1,在900℃下烧结2h,该陶瓷材料的介电常数εr=9.002,品质因数与频率之积Q×f=11.76×104 GHz,谐振频率温度系数τf=-55×10-6/℃。在此基础上采用w(CaTiO3)=5.0%调节其谐振频率温度系数到0,调节后的微波介电性能为εr=10.312,Q×f=5.36×104 GHz,τf约为0     

CaTiO3对Mg2B2O5微波介质陶瓷掺杂改性的研究

采用传统固相反应法制备CaTiO_3掺杂Mg2B2O5微波介电陶瓷。使用X线衍射仪(XRD)、扫描电子显微镜(SEM)和微波介电性能测试等手段,研究了CaTiO_3掺杂对样品微观结构和微波介电性能的影响。结果表明,Mg_2B_2O_5相和CaTiO_3相二者能够共存,随着CaTiO_3掺杂量的增加介电常数和谐振频率温度系数会增大,而品质因数会有所下降。当CaTiO_3的质量分数为5%时,样品在1 085℃烧结4h后获得了最佳微波介电性能,即介电常数εr=7.03,品质因数Q×f=42 221GHz,谐振频率温度系数τf=-2.8×10~(-6)℃-1。     

Li_2O-Nb_2O_5-TiO_2微波介电陶瓷掺杂改性研究

采用传统的固相反应法制备Li-Al-B(LAB)掺杂立方晶系Li2O-Nb2O5-TiO2(LNT)微波介电陶瓷。运用XRD、SEM和微波介电性能测试等手段,研究了LAB掺杂对样品烧结性能及微波介电性能的影响。结果表明,在LNT陶瓷中添加LAB,有效促进LNT陶瓷烧结,使材料的介电常数和品质因数显著提高。当掺入LAB的质量分数为4%时,样品在900℃保温2h后烧结致密,并获得最佳微波性能:介电常数εr=18.05,品质因数与频率的乘积Q×f=22 040GHz(f=6.41GHz),频率温度系数τf=-20.74×10-6/℃。     

低温烧结Ba_3(VO_4)_2-xZnMoO_4微波介质陶瓷研究

采用固相反应法制备了Ba3(VO)4-xZnMoO4陶瓷,研究不同ZnMoO4含量对Ba3(VO)4微观结构及介电性能的影响。X线衍射(XRD)测试结果表明,二者兼容性良好,无第二相产生;具有低熔点及相反(负)频率温度系数的ZnMoO4能有效降低Ba3(VO)4的烧结温度,同时调节温度稳定性。当x=8%(质量分数)时,所制陶瓷烧结温度约850℃,相对介电常数εr≈13,品质因数Q×f≈26 400GHz,谐振频率温度系数τf≈+3μ℃-1。     

CuO掺杂对BaZn_2Ti_4O_(11)陶瓷微波介电性能的影响

采用固相反应法制备了CuO掺杂的BaZn2Ti4O11陶瓷,研究了所制陶瓷的物相、微观结构和微波介电性能。结果表明,CuO既可以在晶界处形成低共熔体,导致液相烧结,降低烧结温度40℃,又可使部分Cu2+进入晶格取代了部分Zn2+,增加Q.f值。掺杂质量分数0.5%的CuO在1 160℃烧结2 h所制得BaZn2Ti4O11陶瓷的微波介电性能较佳:相对介电常数εr=29.4,Q.f=50 500 GHz,频率温度系数τf=–35.6×10–6/℃。     

Si取代对BiNbO4烧结及微波介电性能的影响

采用传统固相反应法制备样品,研究了SiO2掺杂对BiNbO4烧结特性、微观结构、介电性能的影响。利用HP8753E网络分析仪测试样品微波性能。实验结果表明,Si取代后样品逐渐出现了三斜相,随着Si取代量的增加,BiNbO4陶瓷的烧结温度升高,晶粒变大、形状变不规则、样品Q值减小、谐振频率温度系数由正值向负值转变。     

CTLA陶瓷微波介电性能及烧结特性研究

采用固相反应法制备了0.65CaTiO3-0.35LaAlO3(CTLA)陶瓷,研究了CTLA陶瓷的物相组成、烧结特性及微波介电特性。结果表明,CTLA陶瓷只含有Ca0.65La0.35Al0.35Ti0.65O3主晶相,不存在第二相。烧结温度在1 380～1 450℃间,陶瓷的微波介电性能最佳,介电常数εr=44.5,频率温度系数τf≈0,品质因数与频率之积Q×f≈43 948GHz。当w(Nb2O5)=10%时能使陶瓷致密化烧结温度降到1 300℃,但微波性能变差,εr=38.3,τf=-2.8×10-6/℃,Q×f=13 260GHz。     

N2气氛烧结Bi1-xGdxNbO4微波介质陶瓷性能研究

采用普通固相合成法制备了Bi1-xGdxNbO4微波介质陶瓷,研究了N2烧结气氛下,Gd部分取代BiN-bO4陶瓷中的Bi对其烧结性能及微波介电性能的影响。结果表明,不同Gd掺杂量的样品,相结构差别不大,均以低温斜方相为主晶相。随着Gd含量的增加,陶瓷样品的烧结温度升高,表观密度和相对介电常数均略有减小,品质因数与频率之积(Q×f)值也会发生变化。当x(Gd)=0.008时,900℃烧结的Bi0.992Gd0.008NbO4陶瓷样品具有较好的介电性能:介电常数rε=43.6(4.3 GHz),Q×f=14 288 GHz(4.3 GHz),谐振频率温度系数τf≈0。     

(Sr_(1-x)Ba_x)La_4Ti_4O_(15)微波介质陶瓷的显微结构及介电性能

采用传统的固相反应法制备(Sr1-xBax)La4Ti4O15(x=0~1,BSLT)微波介质陶瓷,并对其物相组成、晶体结构及微波介电性能进行分析。研究结果表明,Ba2+含量的增加降低了BSLT陶瓷的烧结温度,陶瓷的主晶相为(Sr,Ba)La4Ti4O15,并伴随有第二相La2TiO5的生成。在微波频率下,随Ba2+含量的增加,BSLT陶瓷的微波介电常数εr及品质因数与频率之积Q×f值先增大后减小,谐振频率温度系数τf为(-4~-11)×10-6/℃,优化出(Sr0.9Ba0.1)La4Ti4O15陶瓷具有最佳微波介电性能:εr=47.5,Q×f=31 582GHz,τf=-7.5×10-6/℃。     

半导体器件与工艺综合

利用器件与工艺综合的思想,开发出自顶向下的新的器件和工艺设计方法,实现了该设计方法的MOSPAD软件,并利用MOSPAD系统做出了一定的综合结果. 做出了关于器件与工艺综合的两个实例,即对FIB器件的器件综合和对阱形成工艺模块进行的工艺综合,并证明了自顶向下的器件与工艺综合思想的可行性.     

镜像综合孔径毫米波辐射测量灵敏度

镜像综合孔径可利用较少的天线获得地球遥感所需的高空间分辨率,但是镜像综合孔径辐射测量灵敏度尚未得到深入分析。针对该问题,推导了二维镜像综合孔径辐射测量噪声特性,在此基础上,对一维/二维镜像综合孔径测量灵敏度进行了分析,开展了仿真实验,并与常规综合孔径测量灵敏度进行了分析比较。     

Speech synthesis using AM/FM sinusoids and band-pass noise

In the speech synthesis model presented in this paper, voiced speech is synthesized as the sum of sinusoidally modulated two FM sinusoids corresponding to the first and second formants. Each FM signal is generated such that its amplitude is equal to the formant amplitude, its carrier frequency to the formant frequency or its linear combination, its modulation frequency to the pitch, and its modulation index to one fifth of the carrier to modulation frequency ratio. Unvoiced speech is generated by shifting the center frequency of a low-pass noise with a bandwidth of 1 KHz, to the frequency where the energy of the unvoiced speech is concentrated. The drawbacks of this scheme are that the pitch and the formant frequencies of the FM signals may deviate up to 40% and 9%, respectively, and spurious formants may occur. A hardware implementation can be accomplished by driving a linear analog circuitry which can simply be integrated on a single chip, by a digital computer which supplies voltages at every T = 5 ms corresponding to seven parameter values. Examples of the signals and spectrograms of synthesized speech obtained by both synthesis by analysis and synthesis by rule are given along with a set of rules for text-to-speech synthesis of Turkish. It is observed that the speech synthesized by analysis loses the speaker's identity but it is highly intelligible, while understanding the speech synthesized by rules requires a training period.     

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators

The PICO-NPA system automatically synthesizes nonprogrammable accelerators (NPAs) to be used as co-processors for functions expressed as loop nests in C. The NPAs it generates consist of a synchronous array of one or more customized processor datapaths, their controller, local memory, and interfaces. The user, or a design space exploration tool that is a part of the full PICO system, identifies within the application a loop nest to be implemented as an NPA, and indicates the performance required of the NPA by specifying the number of processors and the number of machine cycles that each processor uses per iteration of the inner loop. PICO-NPA emits synthesizable HDL that defines the accelerator at the register transfer level (RTL). The system also modifies the user's application software to make use of the generated accelerator.The main objective of PICO-NPA is to reduce design cost and time, without significantly reducing design quality. Design of an NPA and its support software typically requires one or two weeks using PICO-NPA, which is a many-fold improvement over the industry norm. In addition, PICO-NPA can readily generate a wide-range of implementations with scalable performance from a single specification. In experimental comparison of NPAs of equivalent throughput, PICO-NPA designs are slightly more costly than hand-designed accelerators.Logic synthesis and place-and-route have been performed successfully on PICO-NPA designs, which have achieved high clock rates.     

激光控制反应合成的实验研究

本文把表面工程领域两种先进技术——燃烧合成涂层技术和激光表面熔覆技术结合起来进行研究,旨在使这两种表面处理技术优势互补,获得一种新的表面处理技术——激光控制反应合成表面熔覆技术。在结合实验的基础上,研究了在铝热自蔓延反应2Al+Fe_2O_3=2Fe+Al_2O_3的反应物中添加合适的稀释剂,使此体系无法自蔓延,再通过激光能量的输入来诱发和控制反应合成,从而实现在钢板表面的激光陶瓷熔覆。     

Domain–Specific High–Level Modeling and Synthesis for ATM Switch Prototyping

ATM switch, the core technology of an ATM networking system, is one of the major products in Fujitsu telecommunication business. However, current gate–level design methodology can no longer satisfy its stringent time–to–market requirement. It becomes necessary to exploit high–level methodology to specify and synthesize the design at an abstraction level higher than logic gates. This paper presents our prototyping experience on domain–specific high–level modeling and synthesis for Fujitsu ATM switch design. We propose a high–level design methodology using VHDL, where ATM switch architectural features are considered during behavior modeling, and a high–level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate–level implementation. Since the specific ATM switch architecture is incorporated into both modeling and synthesis phases, a high–quality design is efficiently derived. The synthesis results shows that given the design constraints, the proposed high–level design methodology can produce a gate–level implementation by MEBS with about 15 percent area reduction in shorter design cycle when compared with manual design.     

RTL综合中子程序的综合方法

本文论述了RTL综合系统中子程序综合方法,针对以赋值语句为核心的中间数据结构,采取嵌入方式或例示方式进行处理,然后进行格式判别、组合逻辑综合及时序逻辑综合.文章给出具体综合算法,并在最后给出运行实例.     

Incorporating testability considerations in high-level synthesis

In this article we propose two novel methods to improve the testability of the designs produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies self-loops in a design generated by a high-level synthesis system and eliminates as many of these loops as possible by altering the register and module bindings. The second method, BINET with test cost, is a binding algorithm that takes the cost of testing into account during the binding phase of the high-level synthesis. The test cost considered in this article is a function of the number of self-loops in the synthesized design. Thus it generates only those solutions that have fewer if any self-loops. Finally we put the two methods together in which we first use BINET with test cost to produce nearly self-loop free designs and we further improve their testability by using the loop-breaking algorithm. We applied these methods to synthesis benchmark circuits and the results of our study, given in this article, show that the designs produced by our method have indeed reduced testability overhead and improved testability.     

微波双工器电路综合

近年微波滤波器多项式综合技被广泛用于微波滤波器的设计,将此技术由双端口网络推广至三端口网络可以实现微波双工器的综合。根据微波网络技术,可以推导得到微波双工器电路等效y参数与S参数的关系,进而得到微波双工器散射参数s11,s21,s31与两个通道单通带微波滤波器散射参数s11,s21的关系。应用推广后的微波双工器电路综合技术可以实现微波双工器的精确、快速综合。经过对比发现,微波双工器多项式综合结果与微波双工器电路建模仿真响应吻合度很好。