Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces

Analog and Mixed Signal (AMS) designs can be formally modeled as hybrid systems [45] and therefore formal verification techniques applicable to hybrid systems can be deployed to verify them. An extension to a formal verification approach applicable to hybrid systems is proposed to verify AMS designs [31]. In this approach formal verification (FV) is carried out on an AMS block using simulation traces from SPICE, a simulator widely used in the design and verification of analog and AMS blocks. A broader implication of this approach is the ability to carry out hierarchical verification using relevant simulation traces obtained at different abstraction levels of a design when modeled in appropriate platforms. This enables a seamless transition of design and verification artifacts from the highest level of abstraction to the lowest level of implementation at the transistor level of any AMS design and a resulting increase in confidence on the correctness of the final implementation. The proposed approach has been justified with its applications to different AMS design blocks. For each design, its formal model and the proposed computational techniques have been incorporated into CheckMate [11] - a FV tool for hybrid systems based on MATLAB and the Simulink/Stateflow framework from MathWorks. A further justification of the proposed approach is the resulting improvements observed in terms of reduced verification time for different specifications in each design.     

Embedded System Level Self-Test for Mixed-Signal IO Verification

This article presents an embedded system level self-test implementation for verification of a peripheral and its connectivity to the system. The self-test enables to perform a test for verifying the IO connectivity from inside the system. The proposed on-chip-testing scheme exploits IC level CMOS testability structures. The IC level DFT structure is verified. The scheme is confirmed by minor silicon overhead. The system level methodology is applied for a peripheral test. The methodology is evaluated by analyzing the response signal and by making a histogram data analysis. The applicability of the methodology is evaluated by comparing it to the existing methods. The article will define the approach, will list the main benefits of this methodology, analyze the laboratory test results and show the changes that need to be implemented in a mixed-signal IC in order to achieve this system level testability.     

激光修整埋入无源元件的最佳设计

当设计具有埋入无源元件的PCB时,必须仔细考虑影响修整生产率和准确性的因素,而采用激光修整是最佳的。     

采用内置于FPGA中的软核CPU加速嵌入式系统设计

当前,嵌入式系统开发工程师面临的挑战有几个方面：一是要找到满足系统应用要求的处理器,同时兼顾降低产品成本,并达到一定的系统性能。二是要能够提供一个比较长的产品周期,以使客户不用担心会产品的过旧或停产等问题。     

嵌入式设计：随着标准一起变小

在减小工业、医疗、消费应用及其它空间关键应用的尺寸方面，压力持续不断，引发了形状系数极小的嵌入式计算平台的新潮流。由于采用开放标准和专有设计，这些新平台为系统设计者提供了日益增多的现成计算和外设模块，以便简化尺寸受限的应用。尽管它们尺寸紧凑，但这些微型系统组件充分利用新计算元件、串行通信和智能散热技术，以交付强大的处理能力和I／O性能。     

时序电路的形式化证明

对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述.本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用Tempura的程序B表示对该电路的特性描述.公式B（∈）P引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式.这样,一旦证明了B（∈）P,就能证明实现满足规格描述.最后,给出了一个例子来说明此证明方法.     

基于重写规则法的形式验证技术

<正> 一、引言 验证逻辑设计正确性的传统方法是模拟(Simulation),然而随着数字电路规模和功能扩大,模拟方法已不能保证设计的正确性。与此相对,形式验证(formal verification)方法通过对电路结构的形式进行检查和比较来完成验证。它不需要模拟,因而,避开了模拟信号指数上升的问题。形式验证是一个静态分析,它比动态的逻辑模拟具有更大的潜力。 形式验证的一种方法是将其视为自动定理证明:已知一些公理和已成立的引理,证明某一表达式与另一表达式是等价的。美国Illinois技术研究所的A.S.Wojcik用AURA自动定理证明系统进行了逻辑设计的形式验证,AURA用归结原理作自动定理证明,由于归结法会产生大量子句,因此,证明的效率不是很高。     

一种面向嵌入式软件体系结构的形式化建模方法

为了解决MARTE（Modeling and Analysis of Real Time and Embedded systems）在建立嵌入式软件模型时不够精确的问题,结合Object-Z和PTA（Probabilistic Timed Automation）的优点,本文提出了一种集成的形式化建模方法--PTA-OZ.该方法不仅能够对嵌入式软件模型的静态语义和动态语义进行精确描述,而且通过模型转换规则,能够将MARTE模型转换为PTA-OZ模型.并对模型转换的语义一致性进行了验证,证明本文方法在转换过程能够保持结构语义和行为语义的一致性.最后通过实例模型描述从嵌入式软件建模到属性检验的过程.     

嵌入式FlashMemory Cell技术

本文分析了目前常用的快闪存储器(Flash Memory)存储单元结构，介绍了一种适用于嵌入的单元结构，存储器阵列设计、可靠性设计技术。     

集成电路形式化验证方法研究

文中给出了形式化验证的基本理论,介绍了VIS综合系统的验证技术和验证流程.以乘法器为实例对组合电路的正确性进行了验证,并与传统仿真结果进行比较,利用自动化验证工具对系统模型的相关属性进行检测和验证.     

嵌入式Flash Memory Cell技术

本文分析了目前常用的快闪存储器(Flash Memory)存储单元结构,介绍了一种适用于嵌入的单元结构,存储器阵列设计、可靠性设计技术。     

智能合约的形式化验证方法研究综述

形式化方法是在安全关键软件系统中被广泛采用而有效的基于数学的验证方法,而智能合约属于安全关键代码,采用形式化方法验证智能合约已经成为热点研究领域.本文对自2015年以来的47篇典型相关论文进行了研究分析,对技术进行了详细的分类研究和对比分析;对形式化验证智能合约的过程中使用的形式化方法、语言、工具和框架进行综述.研究表...     

一种用于密码协议形式化验证的简单逻辑

给出了一个可用于密码协议形式化验证与设计的简单逻辑.该逻辑采用抽象的通道概念表示具有多种安全特性的通信链路,可在比现有认证逻辑的更抽象的层次上对协议进行处理.     

基于ACSL的密码软件形式化验证方法

在分析通用软件形式化验证方法的基础上,这里设计提出了一种专门针对密码软件安全性的形式化验证方法。该方法采用ACSL（ANSI/ISO C Specification Language）语言对密码软件的安全性进行形式化描述,并采用自动证明与辅助证明相结合的方法,能够对软件的实现是否满足了对安全性至关重要的一些密码学特性进行有效验证。还以一个开源openssl实现中RC4算法的软件实现部分为例,给出了对其保险性进行验证的过程与步骤,结果表明了该方法的有效性。     

JOUX三方密钥协商协议的形式化验证方法研究

Security analysis of cryptographic protocols has been widely studied for many years. As far as we know, we have not found any methods to effectively analyze group key exchange protocols for the three parties yet, which did not sacrifice the soundness of cryptography. Recently, Canetti and Herzog have proposed Universally Composable Symbolic Analysis (UCSA) of two-party mutual authentication and key exchange protocol which is based on the symmetric encryption schemes. This scheme can analyze the protocols automatically and guarantee the soundness of cryptography. Therefore, we discuss group key exchange protocol which is based on Joux Tripartite Diffie-Hellman (JTDH) using UCSA. Our contribution is analyzing group key exchange protocol effectively without damaging the soundness of cryptography.     

嵌入式设计中的RFID:你该如何行动?

借助内置RFID阅读器,嵌入式系统就能与带标签的物品交换数据,来创造与环境合拍的一类新应用。FIDFID(射频识别)技术有潜力成为嵌入式系统设计中的一种常见的重要组成部分。除了在库存管理领域的传统作用以外,     

安全协议形式化验证方法综述

安全协议作为确保网络安全的关键技术,其安全性直接决定了网络的安全性能。然而安全协议设计与分析存在着诸多困难,目前采用的主要方法是形式化方法,主要分为模态逻辑的方法、模型检测的方法、定理证明方法3种。这3种方法特性各不相同,试用范围也有所区别,而且这些方法或多或少都存在着一定的缺陷。Applied pi演算是一种专门针对安全协议设计的理论成熟的形式化方法,它的出现为安全协议的分析带来了全新的思路。     

A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs

SystemC has become a de-facto standard language for SoC and ASIP designs. The verification of implementation with SystemC is the key to guarantee the correctness of designs and prevent the errors from propagating to the lower levels. In this project, we attempt translate SystemC programs to formal models and use existing model checkers to implement the verification. The method we proposed is based on a semantic translation method which translates sequential execution statements described as software character to parallel execution ones which are more closely with the implementation of hardware. This kind of conversion is inevitable to verify hardware designs but is overlooked in related works. The main contribution of this work is a translation method which can preserve the semantic consistency while building SMV model for SystemC design. We present the translation rules and implement a prototype tool which supports a subset of SystemC to demonstrate the effectiveness of our method.