An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.     

Improved Linear Cryptanalysis of CAST-256

CAST-256, a first-round AES (Advanced Encryption Standard) candidate, is designed based on CAST-128. It is a 48-round Generalized-Feistel-Network cipher with 128-bit block accepting 128, 160, 192, 224 ...     

全通用AES加密算法的FPGA实现

针对高级加密标准（Advanced Encryption Standard,AES）算法需要兼容不同工作模式以及不同密钥长度的加密需求,提出全通用AES加密算法。该算法通过设计可调节密钥扩展模块和模式选择模块,实现128/192/256位宽的加密,支持ECB/CBC/CFB/OFB/CTR 5种工作模式。基于Xilinx公司的XC7VX690T FPGA综合仿真,资源消耗为1 947 Slices,最高工作频率为348.191 MHz。     

基于FPGA的16位数据路径的AES IP核

提出一种基于FPGA的16位数据路径的高级加密标准AES IP核设计方案。该方案采用有限状态机实现,支持密钥扩展、加密和解密。密钥扩展采用非并行密钥扩展,减少了硬件资源的占用。该方案在Cyclone II FPGA芯片EP2C35F484上实现,占用20 070个逻辑单元（少于60%的资源）,系统最高时钟达到100 MHz。与传统的128位数据路径设计相比,更方便与处理器进行接口。     

一种基于Feistel结构和WTS的分组密码

AES为新的数据加密标准,通过研究分组密码算法加密的整体结构和AES加密算法,文中设计了一种基于Feistel结构和WTS策略的分组密码算法FWTS。 FWTS采用Feistel结构,轮函数借鉴AES的WTS策略,分组长度为256 bits,密钥长度为128 bits,192 bits,256 bits。通过依赖性测试表明,FWTS算法4轮充分满足雪崩效应、严格雪崩准则和完备性。通过不可能差分分析,FWTS算法的6轮不可能差分所需的时间复杂度要大于AES算法的6轮不可能差分的时间复杂度。FWTS算法的安全性不低于AES算法。通过效率测试表明FWTS的加密效率要高于AES。     

FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).     

可重构的串行高级加密标准加解密电路设计

为了进一步提高高级加密标准(AES)算法在现场可编程门阵列(FPGA)上的硬件资源使用效率,提出一种可支持密钥长度128/192/256位串行AES加解密电路的实现方案。该设计采用复合域变换实现字节乘法求逆,同时实现列混合与逆列混合的资源共享以及三种AES算法密钥扩展共享。该电路在Xilinx Virtex-Ⅴ系列的FPGA上实现,硬件资源消耗为1871slice、4RAM。结果表明,在最高工作频率173.904MHz时,密钥长度128/192/256位AES加解密吞吐率分别可达2119/1780/1534Mb·s^(-1)。该设计吞吐率/硬件资源比值较高,且适用支持千兆以太网。     

Reliable advanced encryption standard hardware implementation: 32- bit and 64-bit data-paths

Cryptographic primitives are extensively used in today's applications to provide the desired security. Malicious or accidental faults that occur in the hardware implementations of cryptographic primitives, specifically in this paper the Advanced Encryption Standard (AES), can result in an erroneous output of encryption/decryption process and reduce the reliability of the cryptographic hardware. The use of a suitable fault-tolerant scheme for AES, to recover it from failures or attacks and bring it back to an operational state, is crucial for reliability, and consequently for security purposes. In this paper, two novel online fault-tolerant schemes are proposed for AES. In the proposed fault-tolerant architecture, the round path is modified and divided it into two pipeline stages. The proposed fault-tolerant schemes are based on a combination of hardware and time redundancies, where a new hardware redundancy is proposed for the AES round function and a time redundancy for the hardware of the AES key expansion unit. The presented fault-tolerant schemes are valid for all versions of AES and are independent of its S-box implementation manner. Both ASIC and FPGA implementations of the original and the proposed fault-tolerant AES along with Full TMR (Triple Modular Redundancy) and Full TTR (Triple Time Redundancy) structures are reported as traditional fault-tolerant schemes. It is shown that the first proposed fault-tolerant architecture, named TMRrp&TTRke32, outperforms these approaches and the previous report in the literature in terms of area overhead and therefore power consumption. Also, the other approach, named TMRrp&TTRke64, is better than the other approaches in achieving a trade-off between area overhead and throughput overhead.     

地图数据网络分发的混合加密算法

分析并比较对称加密算法DES, AES和非对称加密算法RSA,结合地图数据网络分发的实际应用,提出散列组合加密算法。该算法具有AES算法的高效性和RSA算法便于进行密钥管理的特点,将数据与密钥混合后传输,增加了加密的安全性。实验结果表明,新算法满足了数据加密的安全性及效率要求。     

ANS-based compression and encryption with 128-bit security

The bulk of Internet interactions is highly redundant and also security sensitive. To reduce communication bandwidth and provide a desired level of security, a data stream is first compressed to squeeze out redundant bits and then encrypted using authenticated encryption. This generic solution is very flexible and works well for any pair of (compression, encryption) algorithms. Its downside, however, is the fact that the two algorithms are designed independently. One would expect that designing a single algorithm that compresses and encrypts (called compcrypt) should produce benefits in terms of efficiency and security. The work investigates how to design a compcrypt algorithm using the ANS entropy coding. First, we examine basic properties of ANS and show that a plain ANS with a hidden encoding table can be broken by statistical attacks. Next, we study ANS behavior when its states are chosen at random. Our compcrypt algorithm is built using ANS with randomized state jumps and a sponge MonkeyDuplex encryption. Its security and efficiency are discussed. The design provides 128-bit security for both confidentiality and integrity/authentication. Our implementation experiments show that our compcrypt algorithm processes symbols with a rate up to 269 MB/s (with a slight loss of compression rate) 178 MB/s.

     

基于小型FPGA的快速AES算法研究

AES算法在实时数据加密中的应用对其处理速度及在FPGA中实现的功耗和成本提出较高要求。针对上述情况,介绍一种基于小型FPGA的快速AES算法的改进方法,通过微处理器完成AES算法中的密钥扩展运算,同时采用共享技术实现加密和解密模块共享同一密钥。实验结果表明,该方法可有效提高处理速度,节省FPGA资源,降低芯片功耗。     

对称加密算法Rijndael及其编程实现

AES是新的分组对称加密算法高级加密标准,源自比利时人Daemen和Rijmen共同设计的Rijndael算法。该算法充分运用了扩散和混淆技术并使用128/192/256 这3种可变长度的密钥,对128bit分组数据进行加密。对这一算法的加密过程进行了介绍,说明其中S盒的生成方法。给出了利用VC++实现AES的主程序。     

Architecture design of high‐efficient and non‐memory AES crypto‐core for WPAN

This paper presents the architecture design of a high‐efficient and non‐memory Advanced Encryption Standard (AES) crypto‐core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (2⁸) to Galois Field GF(((2²)²)²) can significantly reduce the hardware complexity of the SubBytes Transformation (S‐box). Besides, the on‐the‐fly key expansion function is used to replace the RAM‐based, and the new on‐the‐fly key scheduler fully supports AES‐128, AES‐192 and AES‐256. Moreover, resource‐sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. FPGA experiment results show that the AES core works at 175.75 MHz clock. It takes about 33 clocks and 66 clocks to complete an AES‐128 encryption and decryption, respectively. That is, the corresponding throughputs are 681.7 and 340.85 Mbps. The hardware cost of the AES design is about 2420 slices with 3‐in‐1 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN chips due to its acceptable power dissipation. Copyright © 2010 John Wiley & Sons, Ltd.     

一种电力宽带调制解调器的设计

采用支持宽带接入的调制技术与编码技术的低功耗SoC为核心芯片的解决方案,通过强电与弱电分离电路的设计、电力线调制解调器的组网和传输协议的研究以及相关软件的设计,开发一款电力载波调制解调器PT200D,实现通过电力线实现即插即用的网络传输数据,电力线传输速率达200Mbps,并实现支持128-bit AES数据加密传输技术,同时支持无线64/128/152位WEP加密及WPA-PSK/WPA2-PSK、WPA/WPA2安全机制,有效保障网络安全,为用户提供一种新的网络接入设备。     

A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware

The Advanced Encryption System (AES) is used in almost all network-based applications to ensure security. The core computation of AES, which is performed on data blocks of 128 bits, is iterated for several rounds, depending on the key size. The strength of AES is proportional to the number of rounds applied. So far, the number of rounds is fixed to 10, 12 and 14 for a key size of 128, 192 and 256 bits respectively. Most cryptographers feel that the margin between the number of rounds specified in the cipher and the best known attacks is too small. On the other hand, it is clear that the overall efficiency of a given AES implementation is inversely proportional to the number of rounds imposed. In this paper, we propose a very efficient pipelined hardware implementation of AES-128. Besides, we show that if the required number of rounds must increase to defeat attackers, the proposed implementation stays efficient.     

Lightweight implementation of SILC,CLOC, AES-JAMBU and COLM authenticated ciphers

Authenticated encryption schemes provide both confidentiality and integrity services, simultaneously. CAESAR competition will identify a portfolio of authenticated ciphers, which is expected to be suitable for widespread adoption and offers advantages over AES-GCM. An important criterion for selecting the final candidates, besides security, is the hardware performance in resource-limited environments. In this paper, SILC, CLOC, AES-JAMBU, and COLM authenticated ciphers have been selected from the third round of the CAESAR competition for hardware evaluation. The main reasons to choose these schemes are their lightweight design, sufficient security level, and the use of the AES algorithm as their underlying block cipher. To the best our knowledge, it is the first time that an 8-bit lightweight architecture which is compatible with API v2 is presented for the selected schemes. To implement AES, the Atomic-AES v2 which is one of the smallest implementations has been adopted according to the requirements of the selected schemes. Furthermore, to reduce the area in the hardware implementation, several techniques are used, including implementing one AES core in the datapath, sharing registers to store intermediate values, implementing the tweak functions with the shuffling of wires, and implementing doubling on the GF(2¹²⁸) with 8-bit architecture to construct the higher-order multipliers. The implementation results are presented on ASIC and FPGA platforms. The proposed architecture for each scheme on the two platforms is similar, but different optimization techniques are used for each platform, e.g. the AES S-box is implemented as ROM-based and logic-based on FPGA and ASIC, respectively. The comparing of the results with 128-bit implementations shows that the area on FPGA and ASIC is reduced up to 65% and 88%, respectively. The results of the current study demonstrate that AES-JAMBU has the lowest hardware area and the highest throughput and performance on both platforms. Besides, CLOC has the highest area reduction on both platforms, compared with those of the 128-bit implementations.     

AES算法优化及其在ARM上的实现

为了提高高级加密标准（AES）算法在ARM上的执行效率,针对明文长度和密钥长度均为128位的AES算法,提出了一种在ARM上高效运行并且占用较少ROM空间的实现方案。S盒采用即时计算的方法生成,将列混合和逆列混合修改为针对32位字的操作,密钥扩展采用即时密钥扩展。在S3C2440处理器上实现的实验结果表明,AES算法的优化方案可以在ARM处理器上高效运行并占用了较少的ROM空间。该方案可以应用于存储空间较小的嵌入式系统中。     

基于DES及其改进算法的文件加密系统

随着信息技术的飞速发展,信息安全问题已成为当今社会所面临的重要问题。数据加密标准（DES）因其较高的安全性而被广泛应用于各个行业领域,但是深入的研究证明该算法存在诸多不足。文中在已有的DES算法及其改正算法的基础上,提出了一种新的方法。该方法综合利用了三重DES算法与独立子密钥算法的优点,把原来的64位密钥扩展为128位,通过双重加密增强了加密强度,同时采用局部密钥独立的特性提升加密强度和效率。基于所提出的加密技术,设计并实现了一个加密系统,针对.word、.pdf、.mp3等格式的文件进行了测试,结果证明该系统可行且有效。     

腹膜透析远程监控系统信息安全的研究与设计

针对腹膜透析远程监控系统的数据信息安全问题,研究了基于MD5不可逆加密和AES对称数据加密方式的加密技术,对于用户登录密码进行MD5加密,对网络传输的数据使用Rijndael候选算法利用128位密匙进行加密,同时采用了超级管理员、管理员和普通用户的三级用户权限管理技术和面向连接的TCP网络通信协议,从而实现了对远程监控系统管理用户信息和网络传输数据的保护,有效提高了腹膜透析远程监控系统数据信息的安全性.     

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power.