Characteristics of transparent ZnO based thin film transistors with amorphous HfO2 gate insulators and Ga doped ZnO electrodes

Coplanar type transparent thin film transistors (TFTs) have been fabricated on the glass substrates. The devices consist of intrinsic ZnO, Ga doped ZnO (GZO), and amorphous HfO₂ for the semiconductor active channel layer, electrode, and gate insulator, respectively. GZO and HfO₂ layers were prepared by using a pulsed laser deposition (PLD) and intrinsic ZnO layers were fabricated by using an rf-magnetron sputtering. The transparent TFT exhibits n-channel, enhancement mode behavior. The field effect mobility, threshold voltage, and a drain current on-to-off ratio were measured to be 14.7 cm²/Vs, 2 V, and 10⁵, respectively. High optical transmittance (> 85%) in visible region makes ZnO TFTs attractive for transparent electronics.     

Vertical organic field effect transistor using sulfonated polyaniline/aluminum bilayer as intermediate electrode

We report a vertical organic field effect transistor using a bilayer formed by sulfonated polyaniline (SPAN) film and a thin Aluminum layer as the intermediate electrode. The device uses p-Si as gate, SiO₂ as gate insulator, SPAN/Al bilayer as drain, C₆₀ fullerene as channel and Ag as the source (top electrode). This device works at low voltages driving high current densities for organic field effect transistors, between source and drain, of the order of microamperes, with the additional advantage that the modulation occurs at both negative and positive gate voltages.     

In–Ga–Zn–O thin film transistor with HfO2 gate insulator prepared using various O2/(Ar + O2) gas ratios

We have investigated the effect of the deposition of an HfO₂ thin film as a gate insulator with different O₂/(Ar + O₂) gas ratios using RF magnetron sputtering. The HfO₂ thin film affected the device performance of amorphous indium–gallium–zinc oxide transistors. The performance of the fabricated transistors improved monotonously with increasing O₂/(Ar + O₂) gas ratio: at a ratio of 0.35, the field effect mobility of the amorphous InGaZnO thin film transistors was improved to 7.54 cm²/(V s). Compared to those prepared with an O₂/(Ar + O₂) gas ratio of 0.05, the field effect mobility of the amorphous InGaZnO thin film transistors was increased to 1.64 cm²/(V s) at a ratio of 0.35. This enhancement in the field effect mobility was attributed to the reduction of the root mean square roughness of the gate insulator layer, which might result from the trap states and surface scattering of the gate insulator layer at the lower O₂/(Ar + O₂) gas ratio.     

Printing Semiconductor–Insulator Polymer Bilayers for High‐Performance Coplanar Field‐Effect Transistors

Source–semiconductor–drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next‐generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross‐talk among different devices, and simplify the fabrication process of circuits. Here, a one‐step, drop‐casting‐like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3‐hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO₂ dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor–insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor–insulator bilayer structure is an ideal system for injecting charges into the insulator via gate‐stress, and the thus‐formed PS electret layer acts as a “nonuniform floating gate” to tune the threshold voltage and effective mobility of the transistors. Effective field‐effect mobility higher than 1 cm² V^?1 s^?1 with an on/off ratio > 10⁷ is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits.     

Pulsed laser deposition and characterization of Hf-based high-k dielectric thin films

The continuous downward scaling of the complementary metal oxide semiconductor (CMOS) devices has enabled the Si-based semiconductor industry to meet the technological requirements such as high performance and low power consumption. However, the ever-shrinking dimensions of the active device, metal-oxide-semiconductor-field-effect-transistor (MOSFET), in the circuit create other physical challenges. The industry standard SiO₂ for the gate region is reaching to its physical limits. New materials with higher dielectric constant are needed to replace the silicon dioxide in these gate regions. One of the candidates for this replacement is Hf-based oxides. In this project, we have used pulsed laser deposition (PLD) to synthesize Hf-based high-k dielectric films on Si single crystal substrates with varying deposition parameters and mixtures of HfO₂ and ZrO₂ then used X-ray absorption fine-structure spectroscopy (XAFS) in order to probe the local structure around the Hf metal. The local structural information extracted through XAFS has been correlated with the deposition parameters such as the substrate temperature and the HfO₂, to ZrO₂ ratio in the mixtures.     

Study of carbon nanotube field effect transistors performance based on changes in gate parameters

Carbon nanotubes are known as an interesting material to be used in the next generations of electronic technology, especially at nano regime. Nowadays, carbon nanotube field effect transistor or CNTFET is one of the promising devices for future electronic applications. A CNTFET which uses carbon nanotube as channel or source/drain region is the most promising candidate for replacing the current silicon transistor technology. The study of modern manufacturing approach and impact of device parameters on its performance is one of the important research fields in nanoelectronics. In this paper we study some aspects of changes in gate parameters at different channel diameters. This paper shows that for small values of diameter, increasing the dielectric constant of gate insulator doesn't help to improve the performance as value of dielectric constant of gate insulator reaches a certain amount. Also, increasing the oxide thickness of gate insulator doesn't always decrease transistor performance. For high diameter values, increasing the thickness up to a certain value improves the transistor performance.     

Effects of N2-annealing conditions on the sensing properties of Pt/HfO2/SiC Schottky-diode hydrogen sensor

Hafnium oxide (HfO₂) used as the gate insulator of metal-insulator-SiC Schottky-diode hydrogen sensors is annealed in nitrogen at different temperatures and durations for achieving a better performance. The hydrogen-sensing properties of these samples are compared with each other by taking measurements under various temperatures and hydrogen concentrations using a computer-controlled measurement system. The sensor response of the device is found to increase with the annealing temperature and time because higher annealing temperature and longer annealing time can enhance the densification of the HfO₂ film; improve the oxide stoichiometry and facilitate the growth of an interfacial layer to give better interface quality, thus causing a significant reduction of the current of the sensor under air ambient. The effects of hydrogen adsorption on the barrier height and conduction mechanism of the devices are also investigated.     

Direct observation of crystallization of HfO2 promoted on silicon surfaces in gate dielectric stacks

High-angle annular dark-field scanning transmission electron microscopy was used to investigate the crystallization mechanism of amorphous hafnium dioxide (HfO₂) layers in gate stacks (polysilicon/HfO₂/SiON/Si substrate). A 0.9-nm-thick HfO₂ layer remained amorphous with a uniform thickness on annealing at 1050 °C. In contrast, crystalline islands with a cubic structure formed when a 1.8-nm-thick HfO₂ layer was annealed. These islands had commensurate interfaces with both the silicon substrate and the polysilicon film. These results suggest that crystallization is promoted on a silicon surface.     

Device degradation behavior and polysilicon film morphology of thin film transistors fabricated using advanced excimer laser lateral solidification techniques

The degradation of polysilicon thin film transistors fabricated in films obtained using variations of advanced through-mask excimer laser anneal sequential lateral solidification (SLS) schemes was investigated. The morphology and grain structure of these 50 nm thick polysilicon films was studied using SEM and AFM. Very elongated or square-like polycrystalline silicon grains were observed, as shaped by each crystallization technique. Hot carrier stressing measurements, under gate and drain DC biases, were performed and the TFT device parameters and characteristics were extracted for various stressing times. The threshold voltage V_th, subthreshold slope S and transconductance G_m were observed to exhibit shifts with stressing time, indicating some active layer and interface degradation ascribed to hot carrier injection and trap generation. These shifts depended both on stress conditions and on the fabrication technique used. The hot carrier stressing results thus indicate that the material structure affects the degradation rates of the TFT parameters and trap densities. Furthermore, the device structure and the crystallization conditions, with the resulting film morphology, affect not only the TFT degradation behavior but also other aspects of device performance; the susceptibility to drain current avalanche effects was found to be lower for TFTs in 2^N-shot polysilicon compared to ones in very elongated grain (directional) material.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Study on electrical degradation of p-type low-temperature polycrystalline silicon thin film transistors with C-V measurement analysis

Laser recrystallized low-temperature poly-silicon (LTPS) films have attracted attention for their application in thin-film transistors (TFTs), which are widely used in active matrix display. However, the degradation behavior of p-type LTPS TFTs is not quite clarified yet. In this paper, the instability mechanisms of p-channel LTPS TFTs under DC bias stress have been investigated. From the IV transfer curves, it was observed that LTPS TFT's mobility increases after stress at some bias conditions. This degradation is most likely caused by interface traps between the poly-Si thin film and the gate insulator, as well as the damaged junction of the drain from stress. In this work, the assumption is examined via C-V measurement. It is found that the C_GD curves of the stressed TFT slightly increase for the gate voltage smaller than the flat band voltage V_FB. However, the C_GS curves of the stressed device are almost the same as those before stress. By employing simulation, it is found that the degradation of p-type TFTs under this stress condition is mainly caused by the trapped charges at the interface between the gate and the drain region, which is generated by the high voltage difference applied during DC bias stress.     

Evolution of SiO2/Ge/HfO2(Ge) multilayer structure during high temperature annealing

Use of germanium as a storage medium combined with a high-k dielectric tunneling oxide is of interest for non-volatile memory applications. The device structure consists of a thin HfO₂ tunneling oxide with a Ge layer either in the form of continuous layer or discrete nanocrystals and relatively thicker SiO₂ layer functioning as a control oxide. In this work, we studied interface properties and formation kinetics in SiO₂/Ge/HfO₂(Ge) multilayer structure during deposition and annealing. This material structure was fabricated by magnetron sputtering and studied by depth profiling with XPS and by Raman spectroscopy. It was observed that Ge atoms penetrate into HfO₂ layer during the deposition and segregate out with annealing. This is related to the low solubility of Ge in HfO₂ which is observed in other oxides as well. Therefore, Ge out diffusion might be an advantage in forming well controlled floating gate on top of HfO₂. In addition we observed the Ge oxidation at the interfaces, where HfSiO_x formation is also detected.     

Effect of N2O plasma treatment on the improvement of instability under light illumination for InGaZnO thin-film transistors

This paper investigates the impact of N₂O plasma treatment on the light-induced instability of InGaZnO thin film transistors with a SiO₂ passivation layer deposited by plasma-enhanced-chemical-vapor-deposition (PECVD). For the untreated device, because the deposition of the SiO₂ passivation layer by PECVD causes extra trap states, the anomalous subthreshold leakage current can be attributed to a lowering of the source side barrier due to trap-assisted photogenerated holes. In contrast, the N₂O plasma treatment applied to both the gate insulator and the active layer effectively suppresses the device instability under illumination. In order to clarify the influence of the N₂O plasma treatment, this study investigates a device with treatment of only the gate insulator. This device shows a slight decrease of light-induced subthreshold leakage current. This demonstrates that N₂O plasma treatment on IGZO active layer after its deposition is critical in preventing damage from the subsequent SiO₂ passivation deposition process. In addition, the instability of threshold voltage (V_T) under negative bias illumination stress (NBIS) is significantly improved by the N₂O plasma treatment. Furthermore, a different dark recovery rate follows NBIS for untreated and N₂O plasma-treated devices, indicating different hole-trapping levels exist in the energy band.     

Nonvolatile memory characteristics of solution-processed oxide thin-film transistors using Ag nanoparticles

We developed a nonvolatile memory device based on a solution-processed oxide thin-film transistor (TFT) with Ag nanoparticles (NPs) as the charge trapping layer. We fabricated the device using a soluble MgInZnO active channel on a SiO₂ gate dielectric, Ag NPs as a charge trapping site at the gate insulator-channel interface, and Al for source and drain electrodes.The transfer characteristics of the device showed a high level of clockwise hysteresis that can be used to demonstrate its memory function, due to electron trapping in the Ag NPs charge trapping layer. A large memory window (?V_th) was observed with a forward and backward gate voltage sweep, and this memory window was increased in size by increasing the gate voltage sweep. These results show the potential application of memory on displays and disposable electronics.     

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al₂O₃ appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties.In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO₂ and Al₂O₃ from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic–inorganic interface.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO ₂ gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source C_GS and gate to drain C_GD capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire     

Development of hafnium based high-k materials—A review

The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO₂ in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO₂ emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high-k materials.     

Evaluation of Y2O3 gate insulators for a-IGZO thin film transistors

In this work, Y₂O₃ was evaluated as a gate insulator for thin film transistors fabricated using an amorphous InGaZnO₄ (a-IGZO) active layer. The properties of Y₂O₃ were examined as a function of various processing parameters including plasma power, chamber gas conditions, and working pressure. The leakage current density for the Y₂O₃ film prepared under the optimum conditions was observed to be ~ 3.5 × 10^− 9 A/cm² at an electric field of 1 MV/cm. The RMS roughness of the Y₂O₃ film was improved from 1.6 nm to 0.8 nm by employing an ALD (Atomic Layer Deposition) HfO₂ underlayer. Using the optimized Y₂O₃ deposition conditions, thin film transistors (TFTs) were fabricated on a glass substrate. The important TFT device parameters of the on/off current ratio, sub-threshold swing, threshold voltage, and electric field mobility were measured to be 7.0 × 10⁷, 0.18 V/dec, 1.1 V, and 3.3 cm²/Vs, respectively. The stacked insulator consisting of Y₂O₃/HfO₂ was highly effective in enhancing the device properties.