Prediction of transmission distortion for wireless video communication: Algorithm and application

In this paper, we develop algorithms for estimating transmission distortion in wireless video communication systems. By leveraging the analytical results obtained in our previous works, we design low complexity algorithms that are capable of estimating transmission distortion accurately. We also extend our algorithm for pixel-level transmission distortion estimation to pixel-level end-to-end distortion estimation. Furthermore, we apply our pixel-level end-to-end distortion estimation algorithm to prediction mode decision in H.264 encoder. Experimental results show that (1) our transmission distortion estimation algorithm is more accurate and more robust against inaccurate channel estimation than existing distortion estimation algorithms; (2) our mode decision algorithm achieves remarkable PSNR gain over the existing algorithms for prediction mode decision in H.264 encoder, e.g., an average PSNR gain of 1.44 dB for ‘foreman’ sequence when Packet Error Probability (PEP) equals 5%.     

Advanced side information creation techniques and framework for Wyner–Ziv video coding

Recently, several distributed video coding (DVC) solutions based on the distributed source coding (DSC) paradigm have appeared in the literature. Wyner–Ziv (WZ) video coding, a particular case of DVC where side information is made available at the decoder, enable to achieve a flexible distribution of the computational complexity between the encoder and decoder, promising to fulfill novel requirements from applications such as video surveillance, sensor networks and mobile camera phones. The quality of the side information at the decoder has a critical role in determining the WZ video coding rate-distortion (RD) performance, notably to raise it to a level as close as possible to the RD performance of standard predictive video coding schemes. Towards this target, efficient motion search algorithms for powerful frame interpolation are much needed at the decoder. In this paper, the RD performance of a Wyner–Ziv video codec is improved by using novel, advanced motion compensated frame interpolation techniques to generate the side information. The development of these type of side information estimators is a difficult problem in WZ video coding, especially because the decoder only has available some reference, decoded frames. Based on the regularization of the motion field, novel side information creation techniques are proposed in this paper along with a new frame interpolation framework able to generate higher quality side information at the decoder. To illustrate the RD performance improvements, this novel side information creation framework has been integrated in a transform domain turbo coding based Wyner–Ziv video codec. Experimental results show that the novel side information creation solution leads to better RD performance than available state-of-the-art side information estimators, with improvements up to 2 dB; moreover, it allows outperforming H.264/AVC Intra by up to 3 dB with a lower encoding complexity.     

Novel rate control scheme for intra frame video coding with exponential rate–distortion model on H.264/AVC

Rate control regulates the output bit rate of a video encoder in order to obtain optimum visual quality within the available network bandwidth and to maintain buffer fullness within a specified tolerance range. Due to the benefits of intra-only encoding, such as less computational cost and less latency, it has been more and more widely used. In this paper, we propose an accurate intra-only rate control scheme for H.264/AVC, which includes a novel complexity measurement and a new rate–distortion (R–D) model. We also propose a linear rate–complexity model which takes the intercept into consideration to reduce the estimation error. The proposed R–D model is integrated by the linear rate–complexity model and an exponential rate–quantization model. Based on theoretical analysis and experimental validation, the proposed scheme has high bits prediction precision, and it can also accurately handle buffer fullness. Compared with JVT-W042, our algorithm achieves higher average PSNR and improves the coding quality up to 0.35 dB.     

A 3D-DCT video encoder using advanced coding techniques for low power mobile device

The three-dimensional discrete cosine transform (3D-DCT) has been researched as an alternative to existing dominant video standards based on motion estimation and compensation. Since it does not need to search macro block for inter/intra prediction, 3D-DCT has great advantages for complexity. However, it has not been developed well because of poor video quality while video standards such as H.263(+) and HEVC have been blooming. In this paper, we propose a new 3D-DCT video coding as a new video solution for low power mobile technologies such as Internet of Things (IoT) and Drone. We focus on overcoming drawbacks reported in previous research. We build a complete 3D-DCT video coding system by adopting existing advanced techniques and devising new coding algorithms to improve overall performance of 3D-DCT. Experimental results show proposed 3D-DCT outperforms H.264 low power profiles while offering less complexity. From GBD-PSNR, proposed 3D-DCT provides better performance by average 4.6 dB.     

Fuzzy quantization based bit transform for low bit-resolution motion estimation

This study proposes a novel fuzzy quantization based bit transform for low bit-resolution motion estimation. We formalize the procedure of bit resolution reduction by two successive steps, namely interval partitioning and interval mapping. The former is a many-to-one mapping which determines motion estimation performance, while the latter is a one-to-one mapping. To gain a reasonable interval partitioning, we propose a non-uniform quantization method to compute coarse thresholds. They are then refined by using a membership function to solve the mismatch of pixel values near threshold caused by camera noise, coding distortion, etc. Afterwards, we discuss that the sum of absolute difference (SAD) is one of the fast matching metrics suitable for low bit-resolution motion estimation in the sense of mean squared errors. A fuzzy quantization based low bit-resolution motion estimation algorithm is consequently proposed. Our algorithm not only can be directly employed in video codecs, but also be applied to other fast or complexity scalable motion estimation algorithms. Extensive experimental results show that the proposed algorithm can always achieve good motion estimation performances for video sequences with various characteristics. Compared with one-bit transform, multi-thresholding two-bit transform, and adaptive quantization based two-bit transform, our bit transform separately gains 0.98 dB, 0.42 dB, and 0.24 dB improvement in terms of average peak signal-to-noise ratio, with less computational cost as well.     

Retinex based visual identicalness detection for videos corrupted by imaging noise

Detecting the visually identical regions among successive frames for noisy videos, called visual identicalness detection (VID) in this paper, is a fundamental tool in video applications for lower power consumption and higher efficiency. In this paper, instead of performing VID on the original video signal or on the de-noised video signal, a Retinex based VID approach is proposed to perform VID on the Retinex signal to eliminate the noise influence introduced by imaging system. Several Retinex output generation approaches are compared, within which the proposed Cohen–Daubechies–Feauveau wavelet based approach is demonstrated to have better efficiency in detection and higher adaptability to the video content and noise severity. Compared with approaches performing detection in the de-noised images, the proposed algorithm presents up to 4.78 times higher detection rate for the videos with moving objects and up to 30.79 times higher detection rate for the videos with static scenes, respectively, at the same error rate. Also, an application of this technique is provided by integrating it into an H.264/AVC video encoder. Compared with compressing the de-noised videos using the existing fast algorithm, an average of 1.7 dB performance improvement is achieved with up to 5.47 times higher encoding speed. Relative to the reference encoder, up to 32.47 times higher encoding speed is achieved without sacrificing the subjective quality.     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.     

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH2_4b-2_4b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm² and dissipation power 23.4 mW.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

Low-harmonic distortion in single-ended and push-pull class E power amplifier by using slotted microstrip lines

In this work, a very low-harmonic distortion with high power-added efficiency (PAE) power amplifier (PA) with slotted microstrip lines is reported. The circuit is a push-pull class E amplifier, terminated with defected structures to improve the spectrum purity and efficiency. The relationship of the second and third harmonic to the fundamental is 70 and 54 dBc, respectively. The amplifier is developed with HBT medium power transistors. The circuit works at 1.8 GHz obtaining a PAE close to 60%, delivering an output power of 24 dBm with a power gain of 13.3 dB.     

Media pattern exhibition mechanism via mobile devices

This paper describes a new methodology of pattern exhibition for digital media that can conceal an imperceptible but recognizable watermark on the media captured with mobile devices. From the human perception, the imperceptible watermark of marked media can preserve the fidelity and readability of the image’s content. With the designed, window-based histogram operation, the embedded pattern of the marked media can be exhibited and recognized visually. That is, the designed mechanism can satisfy the essentials of both visible and invisible watermarking techniques to promote significant pattern sharing and identification for mobile applications. Simulations demonstrate that the peak signal-to-noise ratio (PSNR) of the marked image is superior (around 50–70 dB) to many of the existing watermarking algorithms. The process is of low computational complexity, efficient and can be applied in the real world via mobile devices via inner histogram operation.     

CMOS linear high performance push amplifier for WiMAX power amplifier

In this work a novel and efficient approach is proposed to optimize the linearity and efficiency of power amplifiers used in mobile WiMAX applications. A linear and high performance push amplifier is designed and implemented in 0.18 μm CMOS technology to enhance the linearity of a class-E switched-mode power amplifier. The proposed push amplifier consists of two sections; analog and switching sections. The analog section provides required linearity and the switching section guarantees satisfying total efficiency level. Each block is designed and optimized to meet required specifications. The core power amplifier which is a class-E switched-mode power amplifier is also designed to have maximum possible efficiency. The implemented circuit is simulated using HSPICERF and TSMC models for active and passive elements. The proposed power amplifier provides a maximum output power of 25 dBm and a power added efficiency (PAE) as high as 48% at 2.5 GHz operation frequency and supply voltage of 1.8 V. At 1 dB compression point this PA exhibits 23 dBm of output power with 42% PAE and 4.5% EVM which was appropriate for 64QAM OFDM signals.     

A sub-sampling 4.25 GS/s 3-bit flash ADC with asymmetric spatial filter response

A sub-sampling 3-bit 4.25 GS/s flash ADC with a novel averaging termination technique—asymmetric spatial filter response—in 0.13 um CMOS for impulse radio ultra-wideband (IR-UWB) receiver is presented. In this design, a track and hold (T/H) circuit with self-biased buffer is used to compensate the degradation in amplitude when frequency increases to giga Hz. Averaging termination technique using asymmetric spatial filter response is proposed to relieve the termination offset of the flash ADC. A revised encoder scheme is adopted to solve the problem of different propagation delay. The measurement results reveal that the SFDR and SNDR of the ADC are 26.3 dB and 18.4 dB, respectively, even the input signal frequency is 4.2 GHz. INL and DNL are measured improved to 0.11LSB and 0.18LSB, respectively, when asymmetric spatial filter is used. The power of ADC is 63 mW and the active area is 0.49×0.72 mm². The ADC achieves a figure of merit (FoM) of 2.2 pJ/conversion-step.     

Just noticeable distortion model and its applications in video coding

We explore a new perceptually-adaptive video coding (PVC) scheme for hybrid video compression, in order to achieve better perceptual coding quality and operational efficiency. A new just noticeable distortion (JND) estimator for color video is first devised in the image domain. How to efficiently integrate masking effects together is a key issue of JND modelling. We integrate spatial masking factors with the nonlinear additivity model for masking (NAMM). The JND estimator applies to all color components and accounts for the compound impact of luminance masking, texture masking and temporal masking. Extensive subjective viewing confirms that it is capable of determining a more accurate visibility threshold that is close to the actual JND bound in human eyes. Secondly, the image-domain JND profile is incorporated into hybrid video encoding via the JND-adaptive motion estimation and residue filtering process. The scheme works with any prevalent video coding standards and various motion estimation strategies. To demonstrate the effectiveness of the proposed scheme, it has been implemented in the MPEG-2 TM5 coder and demonstrated to achieve average improvement of over 18% in motion estimation efficiency, 0.6 dB in average peak signal-to perceptual-noise ratio (PSPNR) and most remarkably, 0.17 dB in the objective coding quality measure (PSNR) on average. Theoretical explanation is presented for the improvement on the objective coding quality measure. With the JND-based motion estimation and residue filtering process, hybrid video encoding can be more efficient and the use of bits is optimized for visual quality.     

A receiver aware H.264/AVC encoder for decoder complexity control in mobile applications

Due to the power limitations of mobile devices, high-quality video decoding is still a main concern, because it quickly drains battery. In this paper, an H.264/AVC receiver aware encoder has been designed that (1) takes into account all of the decoder modules of a receiver, unlike existing RAEs that only consider some of these modules and are therefore sub optimal, and (2) is independent of decoder implementations and platforms. Furthermore, a decoder complexity controller has been proposed that reduces the complexity of different decoder modules, while minimum distortion is achieved. Finally, we formulate and solve a generic RAE optimization problem, and apply this solution to control the computational resource allocation at the macroblock level of a RAE. Our experiments indicate that the proposed approach can reduce the complexity of different modules by up to 10 % with no quality degradation. In addition, the average error of the proposed complexity controller is 0.8 %, making the accuracy of the system very close to 1.     

Motion-refined rewriting of H.264/AVC-coded video to SVC streams

In this paper, we discuss motion-refined rewriting of single-layer H.264/AVC streams to SVC streams with multiple quality layers. First, we elaborate on techniques we developed for efficient rewriting of residual data from H.264/AVC to SVC. We investigate if rate-distortion performance can further be improved by extending these architectures with motion refinement techniques, which exploit the inter-layer motion prediction mechanisms available in SVC. For optimum performance, we discuss a fast rate-distortion technique based on Lagrangian relaxation. Although motion refinement in the transform-domain leads to extra distortion in the bitstream, we show that our rate-distortion model successfully takes into account both base and enhancement layer rate and distortion during optimization. Implementation results show that motion-refined rewriting in the transform domain can increase rate-distortion performance, with gains of up to 0.5 dB for the SVC base layer. The presented rewriting architectures significantly reduce the computational complexity when compared to reencoding, with a speed-up by a factor of forty or more, even in the case of motion refinement.     

A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Two UWB LNAs based on a new configuration suitable for low-power and low-voltage applications are presented. The proposed configuration saves bias circuit because of sharing only a bias circuit. In designing LNA-1 good phase linearity property achievement is followed for low-power and low-voltage applications, while in LNA-2 the main concerns are high power gain, by keeping low-power consumption, and small chip area. By taking advantages of resistive-feedback and RLC load, wideband input matching is obtained. Based on the proposed configuration, accompany with complete noise analysis, noise of LNA-2 is highly suppressed and flat noise figure is reaped. The 130 nm CMOS LNA-1 and LNA-2 dissipate 2.95 mW and 6.09 mW, respectively, from 0.7 V supply voltage, without using of forward-body-bias technology. Input return loss of both LNAs is below than ?10.5 dB while LNA-1 achieves average power gain of 9 dB and LNA-2 17 dB. The group-delay variation of LNA-1 is about ±6.1 ps over the band of 3.1–10.6 GHz. The NF of LNA-2 is 2.4–2.89 dB over the whole band of interest.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Compact Brillouin bismuth–gallium–aluminum co-doped erbium doped fiber laser

A single-wavelength Brillouin–erbium fiber laser (BEFL) is demonstrated using high germanium dopant concentration fiber and bismuth–gallium–aluminum co-doped high concentration erbium doped fiber (EDF). A 20-m long high Ge-doped fiber is used to provide nonlinear gains to generate a stimulated Brillouin scattering (SBS), and a 4.3-m long Bi–Ga–Al EDF provides linear gains to amplify the SBS. The relationship between the fiber parameters (dopant concentration, effective area, length and so on) of both linear and nonlinear medium and the output performance was discussed. The BEFL power increases as the effective area of the high Ge-doped fiber decreases. There is an optimum length in the high Ge-doped fiber which is 20-m long in this paper. The BEFL output power also increases as the output power of the Bi–Ga–Al EDF increases. The output performance increases as the erbium doping concentration increases. It is necessary to get the effective area of the Bi–Ga–Al EDF large enough to decrease the fiber loss. The optimum length in the Bi–Ga–Al EDF is 4.3 m. The BEFL operates at 1563.61 nm, which is upshifted by 0.09 nm from the Brillouin pump (BP). It has a peak power of ?3 dBm and a side-mode suppression ratio of 26 dB. The BP wavelength is tunable within a wavelength range from 1562.5 to 1564 nm. The BEFL has a narrow linewidth. It is suitable for many potential applications, such as optical communication and sensors.