A real time infrared scene simulator

A real time simulator for infrared scenes is required to evaluate the performances of recognition and tracking of information processing machine in seeker. A real time simulator for infrared scenes composed of two Intel i860 processors is described in the paper. We first describe the hardware architecture of our system, then we give out schematic diagram illustrating how to compute the image sequences of infrared scenes based on our hardware system. Finally, experimental results indicate that the simulator can meet the needs of application in practice.     

基于PC/104嵌入式计算机的惯导模拟器设计

在介绍某型飞机任务系统训练模拟器原理的基础上,阐述基于PC/104嵌入式计算机的飞机惯导模拟器的研制方案,给出模拟系统的硬件电路和软件程序设计,最后用某型飞机任务系统训练模拟器进行了组网导航训练测试,测试结果显示该模拟系统性能稳定,简单可靠,满足设计要求.     

Network/hardware cross-layer evaluation for ROHC and packet aggregation on wireless mesh networks

This paper proposes a profile-based network and hardware co-simulation method to investigate the overall performance and real-timing characteristics of a wireless mesh network (WMN) affected by hardware capabilities, speed and complexity. For the sophisticated algorithms to be assisted by a hardware realization, we adopt the RObust Header Compression (ROHC) and packet aggregation that provide high and reliable data transmission over unstable wireless links, which is proven in the preliminary works. To verify the hardware support needs to get the benefit of the two algorithms, we measure the ROHC processing time from Intel Pentium 4 and RouterBOARD, and identify the deterioration of sensor throughput and successful voice calls under various NS-2 simulation scenarios. The co-simulation method integrates the network level simulator, NS-2 and hardware level simulator, SystemC. In this approach, we first insert the modules of ROHC and packet aggregation algorithms into the network simulator hierarchy, and measure the packet arrival times. Then, the corresponding hardware architecture is designed by SystemC for profiling the hardware delay appeared in encoding and decoding packets. The hardware is suitably designed to reduce the complexity and make a sufficient speedup in the packet processing. Finally, the traced hardware delays are applied into the network level simulator to extract real-timing WMN behaviors changed by the hardware operations in each mesh router.     

Fast and scalable lock methods for video coding on many-core architecture

Many-core processors are good candidates for speeding up video coding because the parallelism of these applications can be exploited more efficiently by the many-core architecture. Lock methods are important for many-core architecture to ensure correct execution of the program and communication between threads on chip. The efficiency of lock method is critical to overall performance of chipped many-core processor. In this paper, we propose two types of hardware locks for on-chip many-core architecture, a centralized lock and a distributed lock. First, we design the architectures of centralized lock and distributed lock to implement the two hardware lock methods. Then, we evaluate the performance of the two hardware locks and a software lock by quantitative evaluation micro-benchmarks on a many-core processor simulator Godson-T. The experimental results show that the locks with dedicated hardware support have higher performance than the software lock, and the distributed hardware lock is more scalable than the centralized hardware lock.     

Implementation of a Markov Chain Monte Carlo Based Multiuser/MIMO Detector

Multiuser/multiple-input–multiple-output detectors that use Markov chain Monte Carlo (MCMC) simulation techniques to obtain likelihood of information bits have been developed recently. In this paper, we explore the implementation details of one such detector and present an efficient hardware architecture of it. The first step in development of this architecture is to derive a log-domain version of the Gibbs sampler, an efficient method of obtaining samples of MCMC simulator. This formulation is numerically stable and can operate with low precision. The log- domain formulation also lends itself to a hardware architecture that involves only addition, subtraction, and compare operations. Moreover, pipelining is introduced in the proposed architecture straightforwardly. We also explore the word-length requirement of the developed architecture through computer simulations.      

A hardware accelerator for two-dimensional image analysis

This paper describes the architecture and operation of a new hardware accelerator called MultiRing for performing various geometrical operations on two-dimensional image space. This hardware architecture is shown to be applicable for design rule checking in VLSI layout and many image processing operations including noise suppression and contour extraction. It has both a fast execution speed and extremely high flexibility. Each row data stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 20 basic instructions each ring cycle, which gives MultiRing maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of MultiRing was confirmed by successfully running a software simulator having one-to-one structural correspondence to the MultiRing hardware.     

一种高效雷达信号模拟器

为了给某些雷达信号处理算法的研究提供一种有效验证手段,设计此款雷达信号模拟器。系统基于DSP＋FPGA＋DDS架构：以DSP为核心,将AD9957作为基本目标信号产生器,在DSP的控制下FPGA产生基带数据提供给上变频芯片AD9957,完成中频模拟信号的产生。该模拟器创新地利用基于乘法器的迭代算法模拟多种类型雷达回波信号,特别适合产生大时宽信号。这种架构在产生多目标,和差信号方面比传统方法更节省硬件资源。结果表明,该系统集成度高,可扩展性强,数据产生方法高效。     

一种基于FPGA的自然场景的实时SAR回波模拟器

为了降低测试雷达系统的成本,设计出一种实时雷达回波模拟器对测试雷达系统的各项参数有很大的帮助。文中采用等效散射体回波模拟算法设计了一种基于FPGA的SAR回波模拟器。通过优化回波模拟算法,实时实现了SAR的回波模拟。实验结果表明,该设计模拟器可以在10.7 s内模拟出一帧1 024×1 024的自然场景的回波数据。最后对回波数据成像质量评估,证明了该回波模拟器的正确性。     

汽车驾驶模拟器二自由度运动系统

为汽车驾驶模拟器设计了一种二自由度运动系统。该系统采用电动驱动方式,提供仰俯、侧倾两个自由度运动。介绍了该系统软、硬件结构和相关控制算法。其中硬件系统由运动平台和电控系统构成,执行机构采用伺服电机及电动缸。软件系统将汽车运行参数解算成电动缸的控制参数,控制电动缸完成运动控制。平台可以实现汽车运行过程中的大部分体感模拟。     

一种基于ISS的软硬件协同验证环境

讨论了一种面向SOC设计的基于指令级仿真器(ISS)的软硬件协同验证环境。在该环境中,硬件用硬件描述语言来建模,软件用编程语言来编写,使用指令集仿真器和事件驱动逻辑仿真器分别完成对软硬件的仿真,两个仿真过程使用不同的进程并行进行,并通过进程间通信(IPC)实现两个仿真器之间的信息交互。     

Implementation of a real-time frequency-selective RF channelsimulator using a hybrid DSP-FPGA architecture

A low cost frequency-selective RF channel simulator architecture is explored in this paper. The technique of quadrature amplitude modulation (QAM) by independent low-pass filtered white Gaussian noise sources forms a rational function approximation (RFA) to the desired Doppler spectrum for flat Rayleigh fading. To simulate frequency-selective fading, this QAM/RFA architecture may be extended by combining delayed outputs from multiple flat fading generators. In this paper, the noise shaping filter considered is in the form of an infinite-impulse-response digital filter followed by an interpolator (upsampler) using linear interpolation. The performance requirements are those in the standard channel simulator section of TIA IS-55-A. The system is implemented almost entirely in the digital domain by use of IF sampling, with the signal processing performed in a high-end floating-point digital signal processor and a field-programmable gate array. The theoretical performance of the simulator is studied with respect to the TIA standard, and limitations of the hardware prototype are identified. A system capable of simulating 12 delay taps, with a processing bandwidth of 5 MHz, can be built at about one-tenth the cost of commercially available channel simulators of comparable performance     

Hardware Simulator Design for MIMO Propagation Channel on Shipboard at 2.2 GHz

A wireless communication system can be tested either in actual conditions or with a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired radio channel, making it possible to test “on table” mobile radio equipments. This paper presents new architectures for the digital block of a hardware simulator of MIMO propagation channels. This simulator can be used for LTE and WLAN IEEE 802.11ac applications, in indoor and outdoor environments. However, in this paper, specific architectures of the digital block of the simulator for shipboard environment are presented. A hardware simulator must reproduce the behavior of the radio propagation channel. Thus, a measurements campaign has been conducted to obtain the impulse responses of the shipboard channel using a channel sounder designed and realized at IETR. After the presentation of the channel sounder, the channel impulse responses are described and implemented. Then, the new architectures of the digital block of the hardware simulator, implemented on a Xilinx Virtex-IV FPGA are presented. The accuracy, the occupation on the FPGA and the latency of the architectures are analyzed.     

A new wideband high frequency channel simulation system

This paper provides a technical overview of a high frequency (HF) channel simulation system that is applicable to either narrowband or wideband HF channels. Although narrowband models of the HF channel have existed for many years, they are applicable only to a limited set of actual narrowband channel conditions. The need for an HF channel model that is valid for both narrow and wide bandwidths over a more extensive range of channel conditions motivated the research reported in this paper. Wideband propagation, noise, and interference models have been developed and implemented in a real-time digital simulator that utilizes state-of-the-art signal processing hardware with a throughput in excess of 1 mega samples/s. The simulator architecture has the flexibility to permit its application to future simulator designs as faster signal processing components become available. The current simulation system can be used for simulating radio channels other than HF because the propagation, noise, and interference models are implemented in software. This flexibility results in a very powerful test instrument     

片上系统设计中软硬件协同验证方法的研究

讨论一种面向片上系统(SOC)设计的基于指令集模拟器和硬件模拟器的软硬件协同验证方法。该方法能够在SOC设计的早期对整个系统功能进行验证,能够为设计者提供一个纯虚拟的软硬件协同验证环境。重点讨论协同模拟过程中软硬件交互事件的产生和处理方法,以及软硬件模拟器之间的同步和优化方法,并且给出了事件驱动硬件模拟器的协同模拟控制算法。最后给出了一个基于ARM7TDMI的设计验证实例。     

Delay Optimized Architecture for On-Chip Communication

Networks-on-chip (NoC), a new system on chip (SoC) paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh (2DDgl-Mesh) for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 (a network simulator) and CINSIM (a component based interconnection simulator) under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our architecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.     

Ein Beitrag zur Bewertung von Rechnerarchitekturen für Echtzeitsimulationsanwendungen

This paper deals with modelling and evaluation of various multi-processor architectures with the goal to achive simulation in real-time. The example under test is a hydraulic simulator kernel on a multi-DSP platform. Based on this kernel, four different versions are considered in comparison as there are: a) a shared memory architecture, b) distributed memory with direct communication, c) a new hardware extension that supports the update of distributed shared memory and d) static partitioning. Advantages and drawbacks of the various versions are treated in theory and compared with actual measurements.     

无线传感器网络硬件平台的研究与设计

无线传感器网络因其巨大的应用前景而受到学术界和工业界越来越广泛的重视。简要介绍了无线传感器网络的体系结构,着重从硬件平台设计的原则出发,对硬件平台进行了研究和分析,最后提出对硬件平台设计的构想。     

多通道卫星信号模拟器的设计与实现

介绍了多通道卫星信号模拟器的工作原理和关键技术,设计了软件和硬件实现方案。其中软件部分采用VC++6.0完成,硬件部分采用FPGA技术实现,通过计算机串口实现了软硬件之间通信。该系统被成功地应用到卫星导航定位系统的研发过程中,具有了卫星信号模拟器的基本功能,并且增加了卫星信号多普勒效应的模拟,为验证接收机的定位性能、信号跟踪和捕获性能等提供了一个逼真的高动态信号环境。