Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.     

On the universality of inversion layer mobility in Si MOSFET's:Part I-effects of substrate impurity concentration

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10¹⁵ to 10¹⁸ cm^-3). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E_eff) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10¹⁸ cm ^-3. The E_eff dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO₂ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection     

A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}hbox{/}hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ p-HEMTs

We investigated 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In_0.52Al_0.48As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In_0.52Al_0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs produced improved device parameters, including transconductance (G_M), cutoff frequencies (f_T)> and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs fabricated by using the ALET technology exhibited G_M,_Max = 1-17 S/mm, f_T = 398 GHz, and v_sat = 2.5 X 10⁷ cm/s.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon

n-channel MOSFET's with channel lengths from 75 nm to 5 µm were fabricated in Si using combined X-ray and optical lithographies, and were characterized at 300, 77, and 4.2 K. Average channel electron velocities υewere extracted according to the equationupsilon_{e}=g_{mi}/C_{ox}, where gmiis the intrinsic transconductance and Coxis the capacitance of the gate oxide. We found that at 4.2 K the average electron velocity of a 75-nm-channel MOSFET is 1.7 × 10⁷cm/s, which is 1.8 times higher than the inversion layer saturation velocity reported in the literature, and 1.3 times higher than the saturation velocity in bulk Si at 4.2 K. As channel length increases, the average electron velocity drops sharply below the saturation velocity in bulk Si. These experimental results strongly suggest velocity overshoot in a 75-nm-channel MOSFET.     

Silicon MOS transconductance scaling into the overshoot regime

Simulations incorporating velocity overshoot are used to derive the dependence of deep-submicrometer MOS transconductance on low-field mobility μ_eff and channel length L_ch. In contract to strict velocity saturation, saturated transconductance departs from a strict μ_eff/L_ch dependence when overshoot is considered. Constraints on μ_eff derived from conventional scaling laws together with strong μ _eff dependencies in these regimes indicate the importance of low-field inversion layer control and optimization. Transconductance in saturation is shown to approach a well-defined limit for very high μ _eff     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

A mobility model for submicrometer MOSFET device simulations

This paper describes a mobility model for submicrometer MOSFET device simulations. The model includes the quantum effects of electrons in the inversion layer proposed by Schwarz et al. By comparison with experimental data from scaled MOSFET's, the limitation of Yamaguchi's model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. This model can predict the current-voltage characteristics within 5- percent accuracy for scaled MOSFET's down to 0.5 µm.     

Predicting CMOS speed with gate oxide and voltage scaling andinterconnect loading effects

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I_dsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted     

Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N_s=N_s(VG) characteristics of the device toward lower gate voltages     

薄膜双栅MOSFET体反型现象的研究

通过对QM模型的介绍，说明了薄膜双栅MOSFET体反型现象是量子效应的结果，并对QM模型中提出的反型层质心概念进行了剖析，阐述了其重要的物理意义和应用价值。利用反型层质心概念，提出了一组形式非常简单，且与体硅单沟道MOSFET表达式十分相似的薄膜双栅MOSFET亚阈值区反型层载流子浓度和亚阈值电流的表达式。与MEDICI模拟结果的比较证明了其精确性。应用反型层质心及所提出的亚阈值区模型，对薄膜双栅MOSFET体反型现象进行了深入的分析，提出了一个能够较好体现体反型作用的硅膜厚度范围。     

Experimental characterization and modeling of electron saturationvelocity in MOSFETs inversion layer from 90 to 350 K

From saturation transconductance of devices of 0.25-μm CMOS technology, the saturation velocity of electrons (ν_sat) in the inversion layer from 90 to 350 K has been determined. The extracted ν_sat at 300 K was 7.86×10⁶ cm/s, which is significantly lower than that of bulk silicon (ν_sat-blk) and has a much weaker temperature dependence. The ratio ν_sat-blk /ν_sat is 1.27 at 300 K, and is increased to 1.68 at 90 K. Consistent values of ν_sat have been determined for devices of three vastly different MOS technologies, demonstrating the technology independence of ν_sat. The results are useful for developing and testing theoretical carrier transport models, and are of practical importance in estimating the ultimate speed performance of surface MOSFETs. An empirical model for ν_sat as a function of temperature has also been derived for application in predictive device simulation     

Dynamical model of Nd:LiNbO3 waveguide lasers

The aim of this work is to investigate theoretically the dynamical characteristics of Nd:LiNbO₃ waveguide lasers. A novel theoretical model to describe the laser dynamics has been developed and implemented; it has the capability to take into account the transversal dynamics of the population inversion, represented with a transversal orthogonal function expansion, and the longitudinal gain saturation effects due to the pump absorption and to the population inversion dynamics. The Nd-doped LiNbO₃ waveguide laser has been considered pumped in the 814 nm wavelength region. The model has been compared with the available experimental data. Results are presented in various operation conditions     

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

The performance and reliability of 0.4 micron MOSFET's with gateoxynitrides grown by rapid thermal processing using mixtures of N2O and O2

We studied the effect of interfacial nitrogen concentration on device characteristics with gate oxynitrides grown from mixtures of N ₂O and O₂ by rapid thermal processing. The performance and reliability of MOS capacitors fabricated by a four mask process and MOSFET's fabricated by a 0.4 μm twin-well process were examined. No degradation of the current drive of n- and p-MOSFET's in the linear and the saturation region was observed due to oxynitridation. The reliability of gate dielectrics represented by charge-to-breakdown for substrate injection and hot carrier immunity of n-MOSFET's is improved with increasing interfacial nitrogen concentration     

A study of quantum interference fluctuations in deep sub-μmMOSFET's under cryogenic conditions

We investigated the phase coherence length, l_φ, in large Si-MOSFET's fabricated using current process technology, with a particular emphasis on highly doped silicon substrates, and then studied the effects of quantum conductance fluctuations in deep sub-μm MOSFET's, with channel length comparable to l_φ. We identified, in a 0.2 μm MOSFET, universal conductance fluctuations in the strong inversion regime and conductance fluctuations due to variable range hopping in the weak inversion regime. The drain bias dependence of these fluctuations indicates clearly that they become a serious concern only at drain voltages lower than 10 mV. Therefore, even if the wave nature of electrons results in quantum conductance fluctuations, it will not lead to a limitation on device miniaturization in future Si-ULSI's     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Inversion layer at the interface of Schottky diodes

An inversion layer can be present at the metal-semiconductor inteface of Schottky diodes with a high barrier and a lightly doped semiconductor. Its influence on the potential distribution and on the electric field distribution (especially on its maximum) is quite important and may be analyzed by means of an analytical model. The current characteristics calculated by the usual models are modified if one takes the inversion layer into account. In particular, the theoretical n of the Schottky diode is smaller than the value obtained from the usual depletion hypothesis, while the barrier height deduced from the experimental saturation current becomes larger. Excellent agreement between the experimental current characteristics of an PtSiSi diode and the combined model of thermionic emission-diffusion is obtained if the inversion layer is considered.