A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.     

A low-power sub 100 ns 256K bit dynamic RAM

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.     

Design of low-power high-speed bipolar frequency dividers

A low-power current mode bipolar frequency divider is discussed. Low-power consumption is achieved owing to the design strategy being based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations     

A high-speed 64K CMOS RAM with bipolar sense amplifiers

A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mW active power and 100 nW standby power. A CMOS six-transistor memory cell is used. The cell size is 18/spl times/20 /spl mu/m, and the chip size is 5.95/spl times/6.84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing, thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the word line delay, the MoSi layer, which has 5 /spl Omega//sheet resistivity, was used for the gate material. The n-well CMOS process is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics. The n-p-n transistor has a 2-GHz cutoff frequency at 1 mA collector current.     

Design of GaAs 1k bit static RAM

A 1 k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to make higher operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of a speed, a power, and an operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far, for practical application in cache or buffer memories.     

Investigation on low-voltage low-power silicon bipolar designtopology for high-speed digital circuits

This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5 V, while maintaining the ability of high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-μm Si bipolar technology. The different versions featured slight modifications in the architecture of the logic cells and the influence on the frequency and supply voltage range of operation has been investigated. Measurements have shown operation from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V and up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively     

A high-speed 1-kbit high electron mobility transistor static RAM

A 1-kbit static RAM with enhancement and depletion-mode devices was designed and fabricated using the high electron mobility transistor (HEMT) technology. The RAM circuit was optimized to achieve ultra-high-speed performance. A subnanosecond address access time of 0.6 ns was measured at room temperature for a total power dissipation of 450 mW. The minimum WRITE-ENABLE pulse width required to change the state of memory cell is less than 2 ns on probe testing. The best chip has 3 bits that failed to function, which corresponds to a bit yield of 99.7 percent. According to the simulation, variations of the threshold voltage inside the memory cell greatly reduce its stable functional range. High-speed operation requires more uniform threshold voltage control to achieve fully operational LSI memory circuits.     

A 25-ns read access bipolar 1 kbit TTL RAM

Design considerations are described for a fast and compact 1024-bit TTL RAM based upon the nonsaturating operation of transistors that has small but stable levels and swings by virtue of `digital resistances'. It is well matched with the very fine pattern processes currently achieved both for metalization and diffusion.     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

A high-speed Hi-CMOSII 4K static RAM

Using advanced high-performance CMOS (Hi-CMOSII) technology and a high-speed circuit technique, a fully static 4096-word by one-bit RAM with typical address access time of 18 ns and power dissipation of 150 mW has been designed. The power-access-time product realized by the design is almost an order of magnitude better than existing NMOS 4K static RAMs. Moreover, to produce low-cost high-density static RAMs, a new redundancy technique utilizing laser shorting of intrinsic polysilicon is proposed.     

A high-speed ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time

An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family.     

A 4096-bit high-speed emitter-coupled-logic (ECL) compatible random-access memory

A 4096-bit pseudostatic MOS random-access memory with emitter-coupled (ECL) compatibility on all inputs including clocks is described. This device exhibits access times of under 80 ns and cycle times of under 150 ns with a standby dissipation of 300 mW. The fully decoded memory is fabricated on a 204/spl times/237 mil silicon chip and is assembled in a 22-lead ceramic dual-in-line package.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

A high-speed 7 bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology     

A 4.5 ns access time 1K /spl times/ 4 bit ECL RAM

An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.     

A low-power, low-cost bipolar GPS receiver chip

A low-power, low-cost, integrated global positioning by satellite (GPS) receiver is described. It operates from a single 2.7-5.5 V supply with a nominal current consumption of only 27 mA. Furthermore, there is no need for expensive external surface acoustic wave (SAW) filters or a radio frequency voltage-controlled oscillator (VCO) module; only a low frequency reference clock (temperature compensated crystal oscillator (TCXO) or crystal), varactor diodes and standard passive elements are necessary for full operation. The chip is compatible with baseband chips requiring 1 fo (1.023 MHz) and 4 fo signal frequencies. The device has been integrated using a 15-GHz silicon bipolar technology