Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

A simplified high-frequency MOS capacitance formula

A simple modification of Lindner's formula for the high-frequency capacitance is proposed which requires neither a numerical integration nor tabulated constants. The formula is accurate to within 1.5% at all biases for uniform doping in the range 10¹⁴/cm³ to 10¹⁸/cm³.     

MOS interface-state density measurements using transient capacitance spectroscopy

The use of a deep-level transient capacitance technique for characterizing the interface properties of an MOS transistor (MOSFET) is discussed. A formulation to calculate interface-state densities is extended from the previous work. Experimental results done with both MOSFET's and MOS capacitors are shown to illustrate the advantages of using a transistor-type structure. The use of MOSFET's provides not only the capability of probing the interface-state densities throughout the bandgap but also eliminates the effects of minority-carrier generation at the interface. The interface-state densities for variously processed MOS structures were investigated. For hydrogen-annealed MOSFET's and MOS capacitors on and orientations of n-type substrates, the interface-state densities were shown to peak near the energies close to the band edges, these corresponding to the measurement temperature where the freeze-out of bull majority carriers occurs. The ability to measure mobile-ion-induced interface states was discussed. The present technique, being a direct differential measurement, has several advantages over the conventionalC(V)technique. It may provide a higher sensitivity and more reliable data on the densities of states. Moreover, the measurement of the densities of states does not necessarily require a determination of surface potential.     

A novel technique for profiling the lateral n- dopingconcentrations of submicron LDD MOS devices

This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n^- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n^- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology     

Frequency and temperature tests for lateral nonuniformities in MIS capacitors

Interface states and lateral nonuniformities produce very similar abnormalities in theC-Vcurves of MIS capacitors. TwoC-Vtechniques are presented here to aid in distinguishing between them. The first technique is based on the frequency dependence of the interface-state capacitance and utilizes the resulting frequency dispersion of the "high-frequency" capacitance in the depletion regime, which occurs in a frequency range typically between a few hundred Hz and 1 MHz. The second method utilizes a freeze-in of carriers in the interface states at liquid nitrogen temperature. A sweep of bias from accumulation into deep depletion at low temperature produces aC-Vcharacteristic which, when compared with the corresponding ideal characteristic for the same semiconductor doping profile, reveals the presence of lateral nonuniformities. A complementary test is provided by temporary illumination of the deep-depleted structure followed by a sweep of bias from inversion into accumulation. A ledge in theC-Vcharacteristic reveals the presence of interface states in the central half of the bandgap.     

Fabrication of silicon MOS devices using X-ray lithography

This paper reports on the high-yield fabrication of silicon MOS transistors using X-ray lithography, measurements and annealing of fast surface states and oxide charges created by X-ray irradiation, and design considerations for submicrometer linewidth X-ray lithography on 7.5-cm diameter silicon wafers.     

A low-noise line-amplified MOS imaging devices

A new MOS imaging device is proposed. It has an amplifier and a correlated double sampling (CDS) circuit at each vertical signal line and an off-chip smear differential gear. The 1/2-in image format, 500×485 pixels, is designed on 1.5-μm CMOS technology, and its fundamental characteristics are analyzed. Random noise is 120 pA, and the aperture ratio is greater than 70%. The smear level is 100 dB. The fixed pattern noise is 2000 pA in the dark, 0.62% in light. Some advantages of this device include a 5-V power supply requirement, a high saturation current, a high signal-to-random-noise ratio, and a low smear level. However, the fixed pattern noise in the dark needs to be lowered for improved performance     

Gate-drain capacitance compensation technique for triode MOS transconductors

It is shown that phase errors in triode MOS transconductors due to gate-drain capacitances can largely be compensated using a crosscoupled quad of transistors with balanced input voltages. The compensation is insensitive to temperature and IC-processing variations and remains good even when the transconductance of the triode MOS transistors is varied.<>     

Small geometry MOS transistor capacitance measurement method using simple on-chip circuits

A method of measuring the gate capacitance of very small geometry devices using simple on-chip circuits is described. Short-channel effects observed in gate capacitance measurements of an MOS transistor with Weff/Leff= 9.2 µm/0.8 µm are presented. Measurement results show that the resolution of the technique is much better than 0.1 fF.     

A general model for interface-trap charge-pumping effects in MOS devices

Interface-trap charge-pumping effect is analysed on the basis of Shockley-Read-Hall theory of trapping, and a model describing the effect for any trapezoidal gate waveform and any reverse biasing source voltage is derived. A simplified version of the model which is valid for identical rise and fall times is also presented and experimentally verified. Experimental results indicate that the spatial variation of surface potential and the modulation of effective gate area by source voltage may strongly influence the charge-pumping current. It is also shown that the effect of gate-area modulation can be characterized directly from charge-pumping measurements.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

A simple model for the overlap capacitance of a VLSI MOS device

A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.     

A linear two-layer model for flat-band shift in irradiated MOS devices

A close-form mathematical expression is derived for the flat-band shift as a function of gate bias during electron irradiation. The model assumes that the charge in the oxide consists of charged layers of variable thickness at each of the two interfaces, depending on voltage polarity and magnitude. The region of extreme linearity which has been observed by numerous investigators and which normally occurs for the relatively small values of gate bias voltages fits this closed-form solution. Analytical results compare favorably with data obtained from 500 and 700 Å thick oxides and with other previously published data.     

Moderate inversion in MOS devices

The region of validity of common approximations for weak and strong inversion is examined. It is shown that at the lower limit of what is often defined as strong inversion region, incremental quantities such as transconductance can be an order of magnitude smaller than the value predicted by using common strong inversion approximations. It is suggested that the limits of validity of widely used approximations for various quantities in weak and strong inversion can be judged by the value of a single parameter, namely the ratio of the inversion layer capacitance to the sum of the oxide capacitance and the depletion region capacitance. It is shown that in the region where this parameter takes values above 0.1, weak inversion approximations are in serious error; similarly, in the region where this parameter takes values below 10, strong inversion approximations are in serious error. The definition of a “moderate inversion region” between the above two limit points is proposed. The width of this region is calculated for a variety of process parameters and values of the quasi-Fermi potential difference, and is found to exceed 0.5 V in many cases. The accuracy of commonly used approximations for the extrapolated threshold voltage is examined.     

Noise in MOS bucket-brigade devices

Previous calculations of noise in bucket-brigade devices (BBD's) have ignored subthreshold leakage current even though BBD's operate in the subthreshold region over most of their useful frequency range. In this work, subthreshold leakage is included in the calculation, but surprisingly, it makes little difference in the end result. The noise spectrum in p-channel BBD's is measured and agrees well with the calculated noise spectrum which includes the effects of correlation between noise packets, imperfect charge transfer efficiency, and output circuitry.     

Limitations of quasi-static capacitance models for the MOS transistor

This letter compares the Meyer [1] and Ward [2,3] quasi-static, intrinsic capacitance formulations for the MOS transistor to an exact, non-quasi-static, incremental analysis of a simplified device. This analysis yields an incremental admittance matrix for the device whose terms are ratios of power series. The Meyer and Ward models are shown to be approximations to this exact solution. Experimental admittance versus frequency data are presented which show good agreement with this theory. The high-frequency modeling of the Ward and Meyer formulations are compared to the data above, and the limitations of these models are discussed.     

Charge pumping in MOS devices

Gate pulses applied to MOS transistors were found to stimulate a net flow of charge into the substrate. Investigation of this effect revealed a charge-pumping phenomeonon in MOS gate-controlled-diode structures. A first-order theory is given, whereby the injected charge is separated into two components. One component involves coupling via fast surface states at the Si-SiO2interface under the gate, while the other involves recombination of free inversion-layer charge into the substrate.