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1.
A simple FET based on a vertical channel configuration is proposed for use as a variable resistor. By tailoring the shape of the channel plan geometry, a large range of log-linear conductance variation may be achieved within a single device. The principle may be used to give other laws of conductance variation and could have application to FETs operating in the power range. 相似文献
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D. M. Yodgorova 《Radioelectronics and Communications Systems》2008,51(5):280-283
This paper deals with researches of phototransistor based on gallium arsenide with tin-doped channel. It is experimentally shown, that in contrast to usual phototransistors with tellurium-doped channels, gate photocurrents are constant, i.e. independent on blocking voltage, and these currents grow with light intensity increase. At that time total photo sensitivity is smoothly controlled by working voltage and it achieves high values, current sensitivity achieves 8.26 × 102 A/W, voltage sensitivity achieves 1.3 × 108 V/W. 相似文献
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Performance of a GaAs power MESFET has been improved significantly by incorporating a pulse-doped InGaAs layer in the GaAs n-channel. InGaAs provides electron transport properties superior to those of GaAs. The doping level of the GaAs layer can be very high, making it a very-high-transconductance device. Moreover, the conduction-band discontinuity at the heterointerface acts as a potential barrier for electron confinement; therefore, the power gain of the FET is significantly improved. The resulting device delivered a power density of 0.6 W/mm with 14% power-added efficiency and 3.5-dB gain at 60 GHz. At a gain of 5.1 dB, power density was 0.4 W/mm 相似文献
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The limiting noise mechanism in field effect transistors is thermal noise of the conducting channel. An analysis of the thermal noise in a linearly tapered inhomogeneous channel FET is presented leading to a solution for the open circuit noise voltage and the short circuit noise current. Improvement in the open circuit noise voltage for the inhomogeneous FET is shown directly from a comparison with the solution for a homogeneous channel FET. 相似文献
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《Electron Device Letters, IEEE》1984,5(9):353-356
This work presents an experimental and theoretical study of the effects of nonrectangular channel geometries on FET electrical characteristics. In particular it is shown that substantial variations of the channel width in vicinity of the drain have significant consequences on the output conductance in saturation. It is, consequently, suggested that the channel geometry can be considered as a further relevant design parameter, to be used in controlling excessive output conductance. 相似文献
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A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (gm) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V gs). That is, the electrons mainly drift in a highly doped channel region at a shallow V gs. A plateau g m region and the maximum g m were achieved at a V gs range of -0.25~+0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I ds) region and nearly equal in the middle and high I ds region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry 相似文献
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Hong W.P. Zrenner A. Kim O.H. Harbison J. Florez L. Derosa F. 《Electron Devices, IEEE Transactions on》1990,37(8):1924-1926
The transport properties of a two-dimensional electron gas in Al 0.3Ga0.7As/GaAs quantum-well delta-doped heterostructures are studied. Electron energy subbands in the quantum well were calculated by a self-consistent method. The FETs having a gate length of 1.3 μm showed a transconductance as high as 340 mS/mm. The FETs also showed a broad plateau of transconductance around its peak, which is not typical in MODFETs 相似文献
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Inaba S. Miyano K. Nagano H. Hokazono A. Ohuchi K. Mizushima I. Oyamatsu H. Tsunashima Y. Ishimaru K. Toyoshima Y. Ishiuchi H. 《Electron Devices, IEEE Transactions on》2004,51(9):1401-1408
In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond. 相似文献
11.
本文着重研究了玻璃栅介质(GGI)氢化非晶硅双极性场效应晶体管(α-Si:HBFET)的转移特性,并比较了SiO_2和SiO_2/α-SiN_x:H栅介质α-Si:HFET的性质.业已发现:(1)硼掺杂和磷掺杂不仅可以人大地提高(GGI)α-Si:HBFET的电流驱动能力,而且可以大大地改善其双极对称性.(2)(GGI)未掺杂α-Si:HBFET可以用来构成静态特性良好的CMOS倒相器.(3)SiO_2栅介质α-Si:HFET具有典型的双极性,但是SiO_2/α-SiN_x:H栅介质α-Si:HFET则不是双极性的. 相似文献
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《Electron Devices, IEEE Transactions on》1987,34(12):2412-2421
The performance capability of AlGaAs/GaAs complementary heterostructure FET (C-HFET) integrated circuits has been evaluated in computer simulations. The study is focused on C-HFET designs in which static currents and gate-leakage currents are sufficiently low to take full advantage of the speed, power dissipation, and logic function capabilities of CMOS-like circuitry. ASTAP computer simulations for loaded NAND and NOR circuits are examined over a wide supply-voltage range at both 300 and 77 K in order to determine the potential of various MODFET, MISFET, and SISFET approaches as well as the prospects of future designs. While performance is limited by FET threshold and gate leakage in present C-HFET approaches, the speed of properly designed 0.7-µm C-HFETs at 300 K is projected to be 3 × faster than comparable 300 K Si-CMOS circuits. C-HFET circuits at 77 K are projected to be more than 4 × faster than 77 K Si-CMOS circuits. It is also found that properly designed C-HFET's could operate at speeds close to those of DCFL n-channel HFET circuits while dissipating only 1/10 of the power. 相似文献
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《Electron Device Letters, IEEE》1980,1(5):83-85
A new structure for a GaAs JFET (P-Column Gate FET) is proposed, employing p-column shaped gates in an active n-layer on a semi-insulating substrate, where the current flows through spaces between the gate columns. It was found that Be ion implantation can produce p-column gates. The FET I-V characteristics are also presented and discussed. 相似文献
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本文叙述了目前在研制功率GaAs FET过程中对器件的输出功率有比较重要影响的诸多因素,例如器件的几何结构、源引线寄生电感、热阻、击穿电压等等,以及对这些因素加以克服或限制的技术。折衷的结果将使所研制的器件具有良好的微波性能。 相似文献
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赵锦林 《固体电子学研究与进展》1984,(1)
本文扼要叙述了单YIG小球双调谐场效应管振荡器的设计及其优点。在2.2~4.8GHz的振荡频率范围内,输出功率大于10mW。在2.2~4.4GHz的倍频程带宽内,输出功率大于20mW,功率起伏小于3dB。 相似文献
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本文发表了一种MIC MES FET放大器的全自动设计方法,通常需要由设计者本人设定的初始考虑和网络拓扑,在这个基于知识库的智能化设计方法中全部可以机助自动确定,因而可提高设计质量。 相似文献
20.
Won Y.H. Yamasaki K. Daniels-Race T. Tasker P.J. Schoff W.J. Eastman L.F. 《Electronics letters》1989,25(21):1413-1414
The current-voltage characteristics of a GaAs vertical field effect transistor (VFET) with an n/sup +/ip/sup +/in/sup +/ planar doped barrier (PDB) launcher has been successfully improved by the optimisation of the launcher structure as well as the reduction of the channel width. Electron-beam direct writing has been used to obtain a small channel width of 0.1 approximately 0.15 mu m, resulting in good pinchoff characteristics. The measured maximum transconductances are 383 and 220 mS/mm at 77 and 300 K, respectively. In spite of a very short channel length (0.1 mu m) and relatively low channel doping density (5*10/sup 16/ cm/sup -3/), a high voltage gain of 15 has been obtained.<> 相似文献