Silicide resistors for integrated circuits

Thin-film resistors are useful in monolithic integrated circuits whenever high sheet resistance (ρs> 1 kΩ/sq) or radiation hardness are required. Silicide resistive films (MoSi2, CrSi2, and Si-Cr) deposited by dc sputtering have been shown to be compatible with monolithic circuit production end require no protective overlayer. Si-Cr films 200-300 Å thick have ρs, and temperature coefficients of resistance (TCR) ranging from about 1 kΩ/sq and +150 ppm/°C (CrSi2) to 20 kΩ/sq and -1400 ppm/°C (17 at % Cr). MoSi2is best suited for resistor applications requiring 100-200Ω/sq. MoSi2films are about 700 Å thick at 200 Ω/sq, compared to < 100 Å for 200-Ω/sq Ni-Cr, and their TCR is -125 ppm/°C. Typical stability for unprotected silicide resistors in TO-5 packages at 200°C, no load, is < ±3 percent during the first 200 h and < ± 0.5 percent during the next 2000 h. The films are stable during short term exposure to high temperatures as encountered during monolithic or hybrid circuit ceramic package sealing.     

Precision thin-film cermet resistors for integrated circuits

The use of thin-film resistors in monolithic integrated circuits is becoming more widespread as the performance requirements imposed upon circuit designers become more stringent. A cermet, consisting of a mixture of Cr and SiO, was selected as a suitable resistor mterial for this purpose because of its compatibility with semiconductor materials and processes, and because of its stability and reproducibility over a wide range of sheet resistance. Cermet films with sheet resistances of 300, 1000, and 2000 Ω/square were flash evaporated on silicon substrates, and resistors were fabricated. The techniques for depositing the cermet films and fabricating the resistors are discussed, and methods for subsequently adjusting the resistors to precise values are described. The properties of the completed resistors are presented in detail.     

Large-value monolithic resistors for micropower integrated circuits

The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. Two major types of field-effect resistor structures are examined and an analysis of the primary factors that determine sheet resistance and parasitic capacitance is presented. Resistor tolerance, linearity, and temperature coefficient are briefly discussed. It is shown that resistors with sheet resistances greater than 50 k/spl Omega///spl square/ and parasitic capacitances less than 0.002 pF/k/spl Omega/ can be readily fabricated in a monolithic structure.     

A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.     

Metallization systems for silicon integrated circuits

An investigation into single and composite layered metallization systems is described with respect to their limitations, possible failure mechanisms, and problems encountered in fabrication. Systems investigated include metals such as chromium, titanium, tungsten, and molybdenum in conjunction with gold. Comparisons are made to conventional aluminum with respect to ohmic contact to silicon, metallurgical reactions, behavior in adverse environmental conditions, method of deposition, and processing difficulties.     

Arsenic-doped polycrystalline silicon film for bipolar integrated circuits

The advantages of the use of As-doped polycrystalline silicon film over that of As-doped glass film in the fabrication of high speed bipolar integrated circuits have been shown. The films have been used for doping buried layer and emitter. Deposition conditions optimized for the As-doped polycrystalline silicon film allows low junction leakage to be attained with low pipe density. During the course of the work the mechanism for the formation of pipes have been suggested.     

Platinum intermetallic resistors for GaAs-based circuits

A simple technique for making intermetallic resistors of sheet resistance around 25 ?/? is described. The resistors were formed by reacting a 300 ? film of platinum with underlying GaAs to completion. PtGa, PtGa2 and PtAs2 phases were identified in the temperature range of 450°C to 550°C investigated. The temperature coefficient of resistivity was of the order of +9.2×10?4°C?1 at 25°C and the resistors appeared to be stable up to current densities of 105 A/cm2.     

n-p-n silicon lateral phototransistors for hybrid integrated optical circuits

An etched mesa silicon lateral phototransistor (EMS-LPT) suitable for detecting the light signal from optical channel waveguides has been designed and fabricated. In this paper both n⁺-p-n⁺uniform base and n⁺-p-p^--n⁺double-diffused EMS-LPT's are reported. The photoactive region of the EMS-LPT is highly localized and can be easily coupled either via an evanescent field or to a grating coupler on a channel waveguide. Light coupling, gain, speed, and signal-to-noise ratio of the device are thereby greatly improved. The fabrication techniques of the EMS-LPT's are compatible with those of MOSFET's, permitting integration of multiple EMS-LPT's and MOSFET load transistors to form optically addressed inverters on the same silicon chip. By flip-chip bonding LiNbO3and silicon substrates and coupling LiNbO3channel waveguides to EMS-LPT's via grating couplers, we produce electrooptic switches with optical input and output.     

Boron-implanted silicon resistors

The sheet resistance of silicon resistors implanted with boron at room temperature has been experimentally determined for doses from 5 × 10¹² to 2 × 10¹⁶ cm^?2. The results have been compared with the V calculated values. Two methods for minimizing the temperature coefficient, TCR, are described, and their merits and disadvantages are discussed. For a 1-kΩ/□ resistor, TCR can be reduced to 1000 ppm/°C by implanting ¹¹B⁺ at low energy, 5–10 keV, and to less than 100 ppm/°C by implanting a suitable dose of Ar⁺ damage. In a two-terminal resistor, the end effect of the total sheet resistance on TCR and on voltage coefficient VCR was also investigated.     

Stacked CMOS circuits integrated in laser-recrystallized silicon films

Laser-recrystallized poly-silicon films are used as a substrate for the integration of MOS transistors and CMOS circuits. Ring oscillators and frequency divider circuits up to 100 transistors operate well with a yield of about 80%. For the integration of stacked CMOS circuits already tested bulk structures are covered with a dielectric layer and a poly-silicon film which is recrystallized at low temperature. The SOI integration technique, with a maximum temperature treatment of 960°C, is employed to manufacture the second active area as a 3-D technology. After the integration process SOI and bulk CMOS transistors operate independently at two different active levels.     

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.     

The use of MOS structure for the design of high value resistors in monolithic integrated circuits

The application of P-channel MOS structure as a resistor is studied in detail. The device operates below saturation. Effective sheet resistances of 7-25 kohms/sq. can be achieved with fair controllability. The linearity of the V-I characteristics will be determined by the biasing conditions. The temperature coefficient of such a resistor is ≈0.3-0.35 percent/°C.     

Sub-quarter micron silicon integrated circuits and single wafer processing

This paper describes the role of single wafer processing in the development of sub-quarter micron silicon integrated circuits (ICs). The issues related to device processing, choice of materials, performance, reliability, and manufacturing are covered. Single wafer processing based rapid photothermal processing (dominant photons with wavelength less than about 800 nm) is an ideal answer to almost all the thermal processing requirements of current and future Si ICs. For process integration, a new model for process optimization based on minimization of thermal stress is proposed. For breaking the sub-100 nm manufacturing barriers, high throughput lithography based on direct writing is a proposed solution.     

FEN filter design using tantalum and silicon integrated circuits

An economical approach to integrated active RC filter design is described. Complex filter networks are broken down into a series of cascadable second-order filter sections consisting of tantalum thin-film RC networks and semiconductor integrated operational amplifiers. Two building blocks are available for any desired frequency within a decade and for any desired filter function (e.g., low-pass, high-pass, band-pass, band-reject, all-pass, etc.). One building block is for low Q realizations and contains one amplifier; the other is for high Q realizations and contains two. The considerable versatility of this approach is obtained by 1) a network synthesis approach based on decomposing a given second-order function into a low Q asymptotic approximation of this function in cascade with an active frequency emphasizing network and 2) by the characteristics of tantalum and silicon integrated circuits.     

Gigaohm-range polycrystalline silicon resistors for microelectronic applications

The objective of this work was to investigate the conduction properties of very high resistance devices formed from undoped chemical-vapor-deposited polycrystalline silicon. Test structures having resistances as high as 600 GΩ at 5 V were fabricated, of a size suitable for microelectronic device applications. Detailed measurements of current-voltage characteristics in the dark and with photoexcitation, the effect of resistor length, and the temperature dependence of resistance, were made. The data is interpreted in terms of a model based on avalanche breakdown of the reverse-biased n⁺-i junction, with the current limited by the remaining quasi-neutral i-region. Theoretical current-voltage curves and the dependence of effective resistance on device length are calculated with the model, showing all the qualitative aspects of the data. Incorporation of gigaohm-range load resistors into a 16K CMOS static RAM cell is described. The work shows the dominant effects of grain boundaries in controlling current transport in undoped polysilicon, providing high-diffusivity paths for impurity diffusion, and apparently determining the reverse breakdown behavior of the junctions present.     

Applications for GaAs and silicon integrated circuits in nextgeneration wireless communication systems

Emerging applications for portable wireless voice and data communications systems are requiring increased data rates and functionality. Meeting cost and performance goals requires careful attention to system level design and partitioning such that appropriate technologies are employed in cost-effective solutions. New circuit designs and techniques are required to meet size, power, and regulatory restrictions. This provides an exciting opportunity for GaAs, silicon, and passive component technologies. This review paper will discuss factors influencing the choice of which technology is best suited to a particular application and present several system level architectures of radio-based communication systems. The paper will illustrate appropriate applications of GaAs, silicon, and passive integrated circuit technologies. A summary is given that highlights the relative strengths and weaknesses of each technology to date     

A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.