Characteristics of Gunn effect device on bulk n-InP

Oscillation characteristics of InP Gunn diodes were studied in a resistive circuit under pulse bias operation. Peak to valley ratio of oscillation current was observed to reach 2.85 at room temperature in planar-type diodes and it stayed constant for a change in ambient temperature from 300 to 450 K. Outside field of a matured domain was found to fall to about 3 kV/cm, which is less than one third of the threshold field.     

Refractory MoSi2and MoSi2/polysilicon bulk CMOS Circuits

Refractory MoSi2and MoSi2/polysilicon have been used to fabricate high-performance 3µm bulk CMOS circuits. Thirty-nine stage ring oscillators, with a fan-in and fan-out of 1, exhibit a switching delay/stage of 1.2 to 1.4ns, and a power-delay product of 0.22 to 0.25pJ at a supply voltage of 5V. The power-delay product ranges from 40fJ for a delay of 9ns to 1pJ for a delay of 0.6ns. Self-checking pattern generator circuits implemented with the same technology show an operating frequency as high as 80 MHz, which corresponds to approximate in-circuit delays of 1.2ns/stage.     

A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

A new polysilicon process for a bipolar device-PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSIs. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an ECL gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 /spl mu/m/SUP 2/ gate area has been achieved. Furthermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000 /spl mu/m/SUP 2/ gate area has been successfully developed.     

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.     

High-bit-rate pulse regeneration and modulation of injection lasers with a planar Gunn device

A simple circuit with a Schottky-barrier-gate Gunn device is presented, which works as a pulse regenerator and modulator for laser diodes. Modulation depth and bias voltages of both Gunn device and laser are separately adjustable, allowing quick adaption for different laser diodes. The circuit was tested with a p.c.m. word at 1.5 Gbit/s.     

Switching properties of highly doped Gunn devices in resistive circuits

The switching behaviour of Gunn devices in the doping range between 7 × 10¹⁴ cm^?3 and 5 × 10¹⁵ cm^?3 acting in resistive circuits is investigated by numerical methods. Carrier transport equations including diffusion are solved for the device in combination with external circuit equations. The switching time is below 100 psec down to less than 10 psec depending on load and doping. The current pulse amplitude is about 40% of the peak current.     

Ring oscillators fabricated in laser-annealed silicon-on-insulator

Both seven and eleven stage n-MOS ring oscillators with 6 µm channel length have been successfully fabricated in scanning. CW argon laser-annealed polycrystalline silicon islands, which are defined prior to the laser annealing step, on oxide substrates. The ring oscillators, which have a fan-out of three, have a switching delay per stage of 58 nsec and a power-delay product of about 7 pJ operating at a supply voltage (VDD) of 5 volts and switching between VDDand ground. The most serious difficulty encountered during circuit fabrication was the deformation of the silicon islands resulting from laser annealing with extensive laser power density.     

Oxide-isolated monolithic technology and applications

Describes the use of selective oxidation and ion implantation to fabricate integrated circuits. The technique of selective oxidation is used to fabricate a `walled emitter' structure as proposed by Panousis. This allows a substantial reduction in transistor size, for a given active area, over standard fabrication techniques. At the same time, parasitic device capacitances are reduced and a considerable improvement in circuit performance is realized. The impurity distribution in the various components is established by the extensive use of ion implantation. It has been demonstrated, experimentally, a 30-pJ resistor transistor-transistor logic gate fabricated using the collector diffusion isolation technology, can be fabricated in oxide isolated monolithic technology with a power-delay product of 6 pJ. Current-mode logic gates have been fabricated with a power-delay product of 1 pJ.     

A GaAs low-power normally-on 4-bit ripple carry adder

The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of 1.56 mW/gate, and a power-delay product of 0.6 pJ. Best speed performance biasing conditions yield a 1.25 ns critical path average propagation delay at a total power dissipation of 180 mW (180 mW excluding buffers), which corresponds to an average gate delay, power consumption and power-delay product of 250 ps, 6 mW, and 1.5 pJ, respectively. Standard cell layout techniques yield an average gate density of 200 gates/mm/SUP 2/, interconnection wiring included.     

High-speed NMOS circuits made with X-ray lithography and reactive sputter etching

The performance of fine line NMOS circuits fabricated with X-ray lithography and reactive sputter etching shows that NMOS can be competitive with other high-speed technologies. Enhancement and depletion mode silicon gate devices with 0.25 µm junction depth, 200 Å gate oxide and 0.7 µm channel length have been used in a 175 ps delay per stage ring oscillator with a 5V power-delay product of .24 pJ and a 600 MHz, 4 stage counter. Slight technology changes also produced a 92 ps delay ring oscillator with a 5V power delay product of 0.53 pJ.     

Bistability and pulsations in semiconductor lasers with inhomogeneous current injection

Bistability and pulsation at microwave frequencies are observed in CW GaAs semiconductor lasers with inhomogeneous current injection. Inhomogeneous current injection is achieved with a segmented contact structure. Crucial to the understanding of the characteristics of this device is the discovery of a negative differential electrical resistance across the contacts of the absorbing section. Depending on the electrical bias condition, this negative differential resistance leads to bistability or light-jumps and self pulsations. A simple model based on conventional rate equations with a linear gain dependence on carrier density explains the observed behavior and suggests a new mechanism in inhomogeneously pumped diode lasers for light-jumps and pulsations which does not depend on the condition for the usually proposed repetitivelyQ-switching. Investigation of the switching dynamics of this bistable optoelectronic device reveals a delay time which is critically dependent on the trigger pulse amplitude and typically on the order of a few nanoseconds with power-delay products of 100 pJ. The observed critical slowing down and its origin is discussed. We also report on the characteristic of this laser coupled to an external optical cavity and we demonstrate successfully that this bistable laser can be used as a self coupled stylus for optical disk readout with an excellent signal to noise ratio.     

(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.     

Short pulse techniques for estimating the temperature and impurity concentration of the active layer of a Gunn diode

A coaxial mount has been designed to allow the short pulse current-voltage characteristics of a Gunn diodes to be measured at various ambient temperatures. The results can be used, in conjunction with c.w. measurements, to estimate the temperature of the active layer and provide a simple means of comparing the thermal properties of both different forms of diode construction and heat sinking. The mount can also be used in an experiment to estimate the impurity concentration of the diode.     

Dependence of normally-off GaAs JFET performance on device structure

The relation between the performance of normally-off JFET's and the Si ion-implantation conditions used to form the channel layer was studied. Static and switching characteristics were investigated for JFET's with three kinds of channel layers; Si implanted at 130 keV to doses of 2,4, and 6 × 10¹²ions/cm². While higher doses gave better static characteristics [Ids, gm, and Ron], higher capacitance degraded the switching characteristics. The optimum parameters were determined for the high-speed switching JFET. With 2-µm gate length, the highest switching speed was 80 ps and the lowest power-delay product was 0.9 fJ. An improved structure satisfying a high-conductance and low-capacitance requirement was successfully fabricated and showed excellent performance for high-speed and low-power logic circuits; the minimum propagation delay was 45 ps and the minimum power-delay product was 3.8 fJ with a delay time of 83 ps.     

An integrated m-out-of-n detection circuit using threshold logic

The design of the integrated 4-out-of-9 detector is based on a threshold logic approach. A differential current-switching circuit configuration is used, and the detector is fully compatible with conventional emitter-coupled logic (ECL). The circuit has a propagation delay of 16 ns and dissipates only 100 mW. The functional power-delay product of 1600 pJ is an order of magnitude below that achieved with an efficient gate design.     

GaAs-MeSFET for digital application

To meet the requirement of defined input and output levels of digital devices, the FET-fabrication process was designed to include the adjustment of the pinch-off voltage in a notched channel structure. The notch is produced by a d.c.-sputter etch, immediately followed by the evaporation of the metals for the Schottky gate. Schottky diodes made from CrAgCrGaAs or AlCrGaAs and annealed at 400°C in forming gas showed a high current stability at forward bias. This allows positive gate bias operation of the FET, which results in pulse sharpening and pulse recovery. A 40 ps switching time was measured including 50% pulse sharpening.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

SOI/CMOS circuits fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates

A CMOS test circuit chip containing six arrays of 360 to 533 parallel transistors, two 31-stage ring oscillators, and two inverter chains has been designed for evaluating SOI wafers prepared by using the graphite strip-heater technique for zone-melting recrystallization of poly-Si films on SiO2-coated Si substrates. One 2-in-diameter wafer has been evaluated in detail by testing all the circuits on each of 98 chips fabricated in the recrystallized film. These measurements reveal a good yield of functional circuits, and most of the failures can be explained by obvious metallization defects. The operating characteristics of each type of circuit are quite uniform from chip to chip. For the ring oscillators, which have a 5 µm gate length and fan in and out of one, at a supply voltage of 5 V the switching delay time is about 2 n s per stage and the power-delay product is 0.2-0.3 pJ per stage.     

Second-breakdown phenomena in avalanching silicon-on-sapphire diodes

A new experimental technique, based on local temperature-induced changes in optical absorption, is used to study second breakdown in avalanching reverse-biased silicon-on-sapphire diodes. The technique allows spatial resolution down to 1 µm and temperature resolution of a few degrees Celsius. Further, used stroboscopically, the technique allows time resolution on the order of nanoseconds. The technique, in conjunction with special constant-current bias circuits and light-emission studies, has been used to elucidate the physical mechanisms underlying second breakdown in avalanching diodes. It is found that second breakdown occurs when the thermally generated leakage current becomes large enough at some localized region of the junction to quench the avalanche there. Under pulse biases, the product of the average pulse power times the square root of the delay timeτDwas essentially constant forτDas short as 1½ ns. However, the junction temperature atτDincreased asτDdecreased, and for very shortτDthe heating was highly nonuniform.