Substrate current in short n-channel MOS transistors

Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law field-dependent correctly predicts the behaviour of the substrate current.     

Generation mechanism of gate leakage current due to reverse-voltagestress in i-AlGaAs/n-GaAs HIGFETs

Device degradation characterized as an increase in the gate leakage current due to continuous reverse-voltage stress was investigated for a 0.35-μm WSi gate i-AlGaAs/n-GaAs doped channel HIGFET (heterostructure insulated-gate field-effect transistor). The gate leakage current, which was dominated by a hole current generated by impact ionization, was found to increase after the application of a gate-to-drain voltage of -6 V for a certain period. The occurrence of the impart ionization was evidenced by the generation of a substrate current and by the negative temperature coefficient of the gate current. The degradation was retarded at an elevated temperature, indicative of hot-carrier-related degradation. The degraded device also showed an ohmic-like gate leakage current. Subsequent annealing at temperatures above 300°C significantly restored the current-voltage (I-V) characteristics. From these observations, a degradation model was developed in which hot holes generated by impact ionization are trapped in the insulator/semiconductor interface, contracting the surface depletion region and thereby increasing the electric field near the gate-edge. A surface treatment using CF₄ plasma was used to suppress the degradation. An FET fabricated using this treatment showed a remarkable decrease in degradation     

SiO$_2$ Barriers for Increasing Gain Events in Solid-State Impact-Ionization Multipliers

A solid-state impact-ionization multiplier (SIM) was designed to amplify signals from arbitrary current sources through impact ionization. A primary application is amplification of signals produced by photodiodes. Photodiodes made from any semiconductor can be wired directly to the SIM's injection node. Planar versions of the SIM suffer from nonideal impact ionization efficiency as a result of injected carriers drifting through the device's depletion region to the output electrode without passing through the highest electric field regions and undergoing ionization events. Low impact ionization efficiency can lead to an increased excess noise factor, higher temperature sensitivity, and higher voltage sensitivity (rate of gain change with respect to applied voltage). This paper describes increasing SIM ionization efficiencies by introducing an insulator between the SIM's injection and output electrodes, effectively directing the carriers into the highest electric field. This method has shown to greatly increase the impact ionization efficiency in simulation and experimental results. Ionization efficiency improvements are demonstrated primarily through decreases in voltage sensitivity.      

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

Observation of fast erase due to enhanced generation of holes caused by electron impact ionization

This letter describes an enhanced erase mechanism in flash memory cells due to impact ionization induced generation of holes. The increased population of holes is initiated by the impact ionization of electrons in the collector-base region of a parasitic bipolar transistor. Electrons injected from the emitter (drain) of a parasitic n-p-n bipolar transistor into the base (substrate) can drift to the collector (source) where the high electrical field in the collector-base space charge region causes impact ionization and carrier multiplication. The impact ionization generated holes that gain enough energy to overcome the oxide barrier can be injected into the floating gate, resulting a very fast erase.     

Substrate current characterization and optimization of high voltage LDMOS transistors

A 30-V LDMOS integrated with a standard 0.15 μm CMOS process is investigated for its double-hump substrate current (I_b) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this second hump of I_b on reliability and device performance is observed. An analytical expression for the second hump of I_b is established by calculating the impact ionization in the drift region according to the electric field distribution obtained by solving Poisson’s equation. The calculated results are compared against the silicon data under various gate/drain bias voltages showing excellent consistency. Additionally, based on the derived expressions for substrate current, the process parameters are optimized achieving much lower substrate current and better reliability performance.     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

Impact ionization in InAlAs/InGaAs/InAlAs HEMT's

The kink effect and excess gate current in InAlAs/InGaAs/InAlAs HEMT's have been linked to impact ionization in the high field region of the channel. In this letter, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel. The channel hole current is then obtained as the quotient of the excess gate current to the gate-voltage-dependent transmission probability. This channel hole current follows the exponential dependence of the ionization constant on the inverse electric field     

耗尽型6H-SiC埋沟PMOSFET电流解析模型

在考虑到杂质的不完全离化作用时,建立了S iC埋沟PM O SFET在发生表面多子耗尽时的电流解析模型。实验结果和模拟结果的一致性说明了此模型的准确性。在300~600 K温度范围表面弱电场的条件下,由于杂质不完全离化作用得到充分体现,因此器件的工作状态有不同于常规模型下的特性;当温度升高时离化率的增大使得杂质的不完全离化作用得不到体现,所以文中模型的结果向常规模型的结果靠近,且都与实验结果接近。同时为了充分利用埋沟器件体内沟道的优势,对埋沟掺杂的浓度和深度也进行了合理的设计。     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

Hot-electron-induced minority-carrier generation in bipolarjunction transistors

The authors report on the observation and analysis of minority-carrier generation in the collector and the substrate of n-p-n bipolar junction transistors as a result of photons which are generated in the collector-base depletion region. Both the substrate current and the additional leakage current peak at V_BE~0.8 V. In the authors' model of the phenomena, the photons induce the generation of carriers both in the depletion region and in the neutral region. The generated minority carriers in the neutral region diffuse and contribute to the substrate current and the junction leakage current. The contribution of the carriers that are generated in the depletion region is not dominant     

高压单边器件的衬底电流再次升高和相关的热载流子注入效应

基于泊松方程和幸运电子模型,推出了适用于高压n型器件衬底电流(ISUB)的公式,并且为模拟和实验测量的结果所验证.普通n型低压器件的热载流子注入(HCI)效应和ISUB相关.因此,ISUB特征曲线的解释理论和基于理论的正确公式表述对于确保器件设计的可靠性尤为重要.高压器件的ISUB随栅极电压变化在峰值后再次升高.然而在普通低压器件的经典特征曲线中,ISUB仅呈现一个峰.高压器件的ISUB再次升高及其相关的可靠性问题成为新的研究热点.最广为接受的理论(Kirk effect)认为,ISUB再次升高是因为栅控沟道内的经典强电场区移动到沟道外n+漏极的边缘.本文与之不同,认为高压器件ISUB的再次升高并非因为经典强电场区的移动,而是因为在n+漏极边缘出现独立的强电场区,和经典强电场区同时并存,这就是双强电场模型.该双强电场模型仅有经典强电场的ISUB方程不适用于高压器件,新的ISUB方程也由此双强电场模型推导出来,公式与实验结果吻合.进一步地,双强电场模型引进了空穴在氧化层的陷落机制,解释了高压器件的热载流子注入效应.     

Efficient Monte Carlo device modeling

A single-particle approach to full-band Monte Carlo device simulation is presented which allows an efficient computation of drain, substrate and gate currents in deep submicron MOSFETs. In this approach, phase-space elements are visited according to the distribution of real electrons. This scheme is well adapted to a test-function evaluation of the drain current, which emphasizes regions with large drift velocities (i.e., in the inversion channel), a substrate current evaluation via the impact ionization generation rate (i.e., in the LDD region with relatively high electron temperature and density) and a computation of the gate current in the dominant direct-tunneling regime caused by relatively cold electrons (i.e., directly under the gate at the source well of the inversion channel). Other important features are an efficient treatment of impurity scattering, a phase-space steplike propagation of the electron allowing to minimize self-scattering, just-before-scattering gathering of statistics, and the use of a frozen electric field obtained from a drift-diffusion simulation. As an example an 0.1-μm n-MOSFET is simulated where typically 30 minutes of CPU time are necessary per bias point for practically sufficient accuracy     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

Temperature dependence of the anomalous leakage current inpolysilicon-on-insulator MOSFET's

A new analytical model is presented for the temperature and bias dependence of the anomalous leakage current based on thermionic field emission via grain boundary traps in the gate-drain overlap region in polysilicon-on-insulator MOSFET's. The existing model based on pure field emission (tunneling) via grain boundary traps does not include a temperature dependence and therefore cannot explain the observed strong temperature dependence of leakage at low gate voltages, as well as the weaker temperature dependence at high gate voltages, which the new analytical model presented in this paper can. Below 150 K, we believe that impact ionization due to the increasing carrier mean free path leads to the observed increase in the leakage current with decreasing temperature. Since the analytical model does not include impact ionization, it cannot model the leakage current at low temperatures     

A 40 nm gate length n-MOSFET

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V.<>     

Temperature dependence of hot-electron-induced degradation in MOSFET's

The temperature dependence of MOSFET degradation due to hot-electron injection has been studied. The slower degradation rate at elevated temperature at fixed stressing bias follows the substrate current level which is reduced mainly by lower localized electric field rather than lower ionization coefficient (both are caused by enhanced phonon scattering). The actual degradation rate at the constant substrate current level is slightly higher at elevated temperatures, indicating an enhanced interface-state generation mechanism. This temperature dependence provides a simple relationship between device degradation and substrate current at various temperatures.     

Influence of impact ionization on the drain conductance inInAs-AlSb quantum well heterostructure field-effect transistors

Using an InAs-AlSb heterostructure field-effect transistor (HFT) structure modified to incorporate an epitaxial p-type GaSb back gate, we measure the impact ionization current caused by hot electrons in the InAs channel. We show that the impact ionization current is only a small fraction of the deleterious increase in the drain current commonly observed in InAs-based transistors. Most of the drain current rise is caused by a feedback mechanism in which holes escaping into the substrate act like a positively charged parasitic back gate leading to an increase in the electron current flow in the channel by an amount that is large compared to the impact ionization current itself. Removal of the impact-generated holes by the epitaxial back gate breaks the feedback loop, and dramatically improves the DC characteristics of the devices, and increases the range of usable drain voltages     

Characterization of soft breakdown in thin oxide NMOSFETs based onthe analysis of the substrate current

We have investigated the properties of soft breakdown (SBO) in thin oxide (4.5 nm) nMOSFETs with measurements of the gate and substrate leakage currents using the carrier separation technique. We have observed that, at lower gate voltages, the level of the substrate current exhibits a plateau. We propose that the observed plateau is due to the Shockley-Hall-Read (SHR) generation of hole-electron pairs in the space charge region and at the Si-SiO₂ interface. At higher voltages, the substrate current steeply increases with voltage, due to a tunneling mechanism, trap-assisted or due to a localized effective thinning of the oxide, from the substrate valence band to the gate conduction band, which becomes possible for gate voltages higher than the threshold voltage. The proposed interpretation Is consistent with the results of measurements performed at different operating conditions, in the presence of light and in the case of substrate reverse bias. The presented results are also useful for characterizing the performance of MOSFETs after SBD     

Inclusion of impact ionization in the backgating of GaAs FETs

It is shown that the familiar threshold behavior of the backgate current of GaAs MESFETs has hysteresis. This is associated with an S-type negative differential conductivity (S-NDC) of the semi-insulating substrate. It is difficult to account for this hysteresis using conventional trap-fill-limited (TFL) theory, and it is attributed to the impact ionization of traps in the substrate. A simple model of this ionization, involving two trap levels, is used to incorporate its effect into an existing analytical model of GaAs FETs. The result is a qualitative interpretation of the backgating characteristics of GaAs MESFETs. The calculations show that a simple combination of two ohmic elements to represent parasitic resistances, and a nonohmic one to represent impact ionization in the substrate, can imitate the observed backgating behavior