Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S₂₁ parameter was measured up to 20 GHz.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection

In this paper, we describe hybrid bonding technology of single-micron pitch with planar structure for three-dimensional (3D) interconnection. Conventionally, underfill method utilizing capillary force was used after the bonding of microbump. However, the filling becomes insufficient in a gap less than 10 μm between chips or bumps. One promising technology is the hybrid bonding technology that microbumps and an adhesive can be simultaneously bonded. To realize a single-micron pitch hybrid bonding, we fabricated a planar structure that consists of 8 μm-pitch Cu/Sn microbumps and a non-conductive film (NCF) by a chemical mechanical polishing (CMP) of resin. After planarization, the Cu/Sn bumps and the NCF were simultaneously bonded at 250 °C for 60 s. Cross-sectional scanning electron microscope (SEM) images and energy dispersive X-ray spectroscopy (EDX) images show that the adhesive resin on the bump surface was successfully removed by the CMP. In addition, SEM images of the bonded sample show that the adhesive filled the 2.5-μm gap between the chip and substrate. The Cu/Sn bumps were properly bonded in a corner on the chip. The proposed bonding method is expected to enable single-micron pitch interconnection for ultra-high density 3D LSI of next generation.     

Creep of thermally aged SnAgCu-solder joints

The creep behaviour of Sn96.5Ag3.5- and Sn95.5Ag3.8Cu0.7-solder was studied specifically for its dependence on technological and environmental factors. The technological factors considered were typical cooling rates and pad metallizations for solder joints in electronic packaging. The environmental factors included microstructural changes as a result of thermal aging of solder joints. Creep experiments were conducted on three types of specimens—flip–chip joints, PCB solder joints and bulk specimens. flip–chip specimens were altered through the selection of various under bump metallizations (Cu vs. NiAu), cooling rates (40 K/min vs. 120 K/min), and thermal storage (24 h, 168 h, and 1176 h at 125 °C). PCB solder joints were studied by using a copper pin soldered into a thru-hole connection on a printed circuit board having a NiAu metallization. Bulk specimens contained the pure alloys. The creep behaviour of the SnAg and SnAgCu solders varied in dependence of specimen type, pad metallization and aging condition. Constitutive models for SnAg and SnAgCu solders as they depend on the reviewed factors are provided.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.     

Numerical study on the bonding tool position, tip profile and planarity angle influences on TAB/ILB interconnection reliability

Tape automated bonding (TAB) is a widely used interconnection technology for high-pincount and fine-pitch IC packaging. In this study, a three-dimensional computational model was developed for analyzing TAB inner lead bonding (ILB) process. This experimental study on the thermomechanical properties of copper leads was achieved using high precision micro-force tensile tests. A stress–stain relation between the copper lead and different temperature ranges was successfully implemented into the finite element model to study large plastic deformation in ILB formation. The resulting ILB lead profile and bump sinking values obtained from the simulations agreed well with the experimental observations from actual manufacturing data with the same bonding parameters. The tool position and lead length effects are analyzed to study the residual stress distribution after ILB. A 10-lead model was developed to study how the tool tip profile and planarity ‘angle affect the co-planarity between the bonding tool and the stage. The numerical results show that the permissible tool profile variance should not exceed 1.25 μm and the acceptable planarity angle is 0.005° to achieve the minimum bump deformation requirement.     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

Reliability of Au bump––Cu direct interconnections fabricated by means of surface activated bonding method

As a room temperature bonding method, surface activated bonding (SAB) method has been introduced to be one of the most appropriate interconnection methods for the next generation of electronic packaging. Thus it is important to study the reliability of SAB interconnection in long term life test.In this paper, interconnections of Au bump and Cu film bonded by SAB method were performed in high temperature thermal aging test. Degradation of properties such as electrical resistance, shear strength of bump and interface microstructure during aging process were studied to investigate the failure mechanism of the interconnection. Intermetallic compound Cu₃Au was found formed at the interface during thermal aging, and it causes evolvement of the properties and failure mode of the interconnection changing in shear test. Results reveal that SAB is suitable for the interconnection between Au bump and Cu film and it is reliable in thermal reliability test.     

Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

The influence of solder volume and pad area on Sn–3.8Ag–0.7Cu and Ni UBM reaction in reflow soldering and isothermal aging

This paper examines various aspects of SAC (Sn–3.8Ag–0.7Cu wt.%) solder and UBM interactions which may impact interconnection reliability as it scales down. With different solder joint sizes, the dissolution rate of UBM and IMC growth kinetics will be different. Solder bumps on 250, 80 and 40 μm diameter UBM pads were investigated. The effect of solder volume/pad metallization area (V/A) ratio on IMC growth and Ni dissolution was investigated during reflow soldering and solid state isothermal aging. Higher V/A ratio produced thinner and more fragmented IMC morphology in SAC solder/Ni UBM reflow soldering interfacial reaction. Lower V/A ratio produced better defined IMC layer at the Ni UBM interface. When the ratio of V/A is constant, the IMC morphology and growth trend was found to be similar. After 250 h of isothermal aging, the IMC growth rate of the different bump sizes leveled off. No degradation in shear strength was observed in these solder bump after 500 h of isothermal aging.     

Characteristic study of anisotropic-conductive film for chip-on-film packaging

Chip-on-film (COF) is a new technology after tape-automated bonding (TAB) and chip-on-glass (COG) in the interconnection of liquid crystal module (LCM). The thickness of the film, which is more flexible than TAB, can be as thin as 44 μm. It has pre-test capability, while COG does not have. It possesses great potential in many product fabrication applications.In this study, we used anisotropic-conductive film (ACF) as the adhesive to bind the desired IC chip and polyimide (PI) film. The electric path was formed by connecting the bump on the IC and the electrode on the PI film via the conductive particles in the ACF. In the COF bonding process experimental-design method was applied based on the parameters, such as bonding temperature, bonding pressure and bonding time. After reliability tests of (1) 60 °C/95%RH/500 h and (2) −20 to 70 °C/500 cycles, contact resistance was measured and used as the quality inspection parameter. Correlation between the contact resistance and the three parameters was established and optimal processing condition was obtained. The COF samples analyzed were fabricated accordingly. The contact resistance of the COF samples was measured at varying temperature using the four points test method. The result helped us to realize the relationship between the contact resistance and the operation temperature of the COF technology. This yielded important information for circuit design.     

Reliability of SnPb and Pb-free flip–chips under different test conditions

This paper presents the results of an experimental study of the lifetime of flip–chip solder joints on low temperature cofired ceramics (LTCC) substrates. Otherwise identical test vehicles were built with SnPb37 and SnAg4Cu0.5 solder. The mean lifetimes of the SnPb37 joints were – depending on test condition and die size – between 637 and 1465 temperature cycles. The failures occurred due to fatigue cracks in the solder. The components soldered with SnAg4Cu0.5 solder showed a significantly longer time until electrical breakdown. A partial stress relief caused by cracks in the metallization layers was identified as one reason for the long time to failure of the lead free solder joints.In the second part of the paper, a model for lifetime prediction of solder joints based on FEM simulation is derived from these results. The absence of underfill simplified the FEM simulation, because the solder is the only material with nonlinear material behavior in the test vehicle. By combining the experimental results with the computer simulation, it is possible to generate equations that permit the prediction of the lifetime of solder joints based on FEM simulations. They could be used to calculate the lifetime for similar flip–chip interconnects. The two common approaches (strain-based or energy-based) for generating such equations are compared. Both approaches were capable of describing the experimental observations.     

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm² and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.     

Cu引线超声键合动态过程有限元模拟

引线键合是电子封装中一种重要的芯片互连技术,其中Cu引线的超声键合是目前研究的热点.利用ANSYS有限元软件建立了包括Cu引线、键合劈刀、焊盘以及芯片在内的超声楔焊模型,采用非线性有限元方法研究冲压和超声振动两个阶段的应力场变化,着重探讨超声振动阶段材料塑性变形量的突变,并分析超声功率改变时焊点结构中应力和应变的变化.     

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.     

基于MCM-D工艺的3D-MCM工艺技术研究

基于MCM-D薄膜工艺,开展了3D-MCM相关的无源元件内埋置、芯片减薄、芯片叠层组装、低弧度金丝键合、芯片凸点,以及板级叠层互连装配等工艺技术研究。通过埋置型基板、叠层芯片组装、板级叠层互连,实现了3D-MCM结构,制作出薄膜3D-MCM样品;探索出主要的工艺流程及关键工序控制方法,实现了薄膜3D-MCM封装。     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

焊料凸点倒装焊技术

介绍了倒芯片面阵式凸点制作、多层陶瓷基板焊盘制作及倒装焊各关键技术 ,并成功地获得了芯片与基板的互连。     

Process improvement of 0.13 μm Cu/Low K (Black Diamond) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.