操作系统级低功耗动态电压缩放算法分析

低功耗的设计已经成为嵌入式系统设计中一个非常重要的方面，而动态电压调度（Dynamic Voltage Scaling DVS）又被认为是降低功耗的一种有效手段。本文对各类针对系统的动态电压缩放算法做了较系统的总结，给出了算法的模型，重点描述了操作系统级的两类动态电压缩放算法——基于间隔和基于任务的动态电压调度算法，概述了针对编译级的任务内动态电压调度算法。文章对三类算法作了分析与比较，由此给出了结论与观点，对以后动态电压缩放算法的研究做了预测。     

Hardware-Software Partitioning for Real-Time Embedded Systems

In this paper, we present an approach to hardware-software partitioning for real-time embedded systems. Hardware and software components are modeled at the system level, so that cost and performance tradeoffs can be studied early in the design process and a large design space can be explored. Feasibility factor is introduced to measure the possibility of a real-time system being feasible, and is used as both a constraint and an attribute during the optimization process. An imprecise value function is employed to model the tradeoffs among multiple performance attributes. Optimal partitioning is achieved through the use of an existing computer-aided design tool. We demonstrate the application of our approach through the design of an example embedded system.     

动态电压调整多处理器实时系统任务调度

动态电压调整DVS（Dynamic Voltage Scaling）是根据处理器电压（速度）降低之后，能量消耗平方级的减少这一原理提出的。文章通过DVS机制在多处理器实时系统中进行任务调度．通过对任务调度中的静态能量管理进行分析，在此基础上提出了一种新的基于DVS的适用于多处理器实时系统中的调度算法。这种新的调度算法是通过对贪婪法调度进行研究，发现其不足．并以此为基础进行改进。结合了动态电压调整的多处理器实时系统任务调度的能量消耗比普通的任务调度能量消耗有了很大的改善。     

Multi-Valued Performance Metrics for Real-Time Embedded Systems

To rapidly explore the design space of a real-time embedded system, it is essential to be able to efficiently analyze the timing behaviors of different system architectures. This includes not only determining if a design can satisfy all the timing constraints but also comparing the timing performance of different designs for tradeoff purposes. Understanding the exact timing behavior of a large system can be computationally prohibitive. Previous work in this area has mostly focused on producing a yes/no answer to the schedulability of a system architecture under the worst-case scenario. This not only often leads to overly pessimistic designs, but also provides no insight as how to rank different architectural designs with respect to their timing performance. In this paper, we present several metrics that may be used to measure the timing performance of a design. The metrics were analyzed using workloads from both real-world task systems and randomly generated task systems. A superior metric has been identified through analysis of large sets of experiments. We also show, through an example, how this metric can be used effectively during a design exploration process.     

Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms

System-on-a-chip platform manufacturers are increasingly adding configurable features that provide power and performance flexibility, in order to increase a platform's applicability to a variety of embedded computing systems. We illustrate the energy benefits of combining the configurable features of voltage scaling and cache way shutdown in a single platform. We describe methods to assist a designer to tune such a platform to a particular software task and to particular energy optimization criteria.     

Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems

In this paper, we combine coarse-grained software pipelining with DVS (Dynamic Voltage/Frequency Scaling) for optimizing energy consumption of stream-based multimedia applications on multi-core embedded systems. By exploiting the potential of multi-core architecture and the characteristic of streaming applications, we propose a two-phase approach to solve the energy minimization problem for periodic dependent tasks on multi-core processors with discrete voltage levels. With our approach, in the first phase, we propose a coarse-grained task-level software pipelining algorithm called RDAG to transform the periodic dependent tasks into a set of independent tasks based on the retiming technique (Leiserson and Saxe, Algorithmica 6:5–35, 1991). In the second phase, we propose two DVS scheduling algorithms for energy minimization. For single-core processors, we propose a pseudo-polynomial algorithm based on dynamic programming that can achieve optimal solution. For multi-core processors, we propose a novel scheduling algorithm called SpringS which works like a spring and can effectively reduce energy consumption by iteratively adjusting task scheduling and voltage selection. We conduct experiments with a set of benchmarks from E3S (Dick 2008) and TGFF () based on the power model of the AMD Mobile Athlon4 DVS processor. The experimental results show that our technique can achieve 12.7% energy saving compared with the algorithms in Zhang et al. (2002) on average.

Peak Power Minimizing Algorithm by Voltage Scheduling

For complicated electronic systems, to ensure high performance and reliability satisfaction, minimizing peak power consumption becomes one of the most important design goals. This paper addresses the problem of variable voltage scheduling on multlprocessor distributed systems, with the goal of shaping the power profile to minimizing peak power. A low peak power algorithm named LPPA is proposed to optimize power distribution via scaling voltage of the tasks on critical regions, based on the comprehensive analysis of how power consumption varies with latency. Compared with previous low peak power techniques, which simply scale voltage of tasks according to their timing critical degree, LPPA additionally take the power profile into count to further decrease the peak power. Experimental results show that the proposed voltage scheduling technique significantly improves the power characteristics over the existing power profile unaware scheduling technique. Meanwhile, energy consumption reduction is also obtained.     

CPS异构分布实时系统中带负载因子的容错调度

介绍了Cyber-Physical Systems的基本内容,给出了基于Cyber-Physical Systems异构分布式中的实时任务系统模型。并在该模型下结合基/副版本备份技术提出了两种适应于Cyber-Physical Systems异构分布式实时环境的启发式容错调度算法:HDLMA算法和HDLFA算法。最后针对这两种算法,分析了算法可调度性,负载均衡性,任务粒度大小对负载均衡性的影响,以及调度阀值对算法可调度性的影响。     

宽带Wilkinson 功分器综合公式的缺陷与改进

首先介绍了3 种宽带Wilkinson 功分器的综合方法,重点阐述了最为常用的Cohn 的设计方法,并指出 随着功分器节数的不断增加,在利用Cohn 的设计公式计算隔离电阻阻值时会产生负数的问题。为此,通过引入一 个调整参数改进Cohn 的设计公式,实现了节数更多情况下隔离电阻阻值的准确计算。在计算功分器各级传输线特 性阻抗的过程中,提出了一种基于MATLAB 程序的多项式化简方法,实现了任意带宽的切比雪夫阻抗变换器参数的 快速计算。此外,还给出了一个8 级到15 级的功分器设计参数表格,作为对Cohn 给出的设计表格的扩展。最后,利 用改进后的设计公式,设计了一个1 ~15GHz 的宽带Wilkinson 功分器。仿真和测试结果证明了这种方法的有效性。     

Design of a hard real-time multi-core testbed for energy measurement

This paper presents a systematic methodology for designing a hard real-time multi-core testbed to validate and benchmark various rate monotonic scheduling (RMS)-based task allocation and scheduling schemes in energy consumption. The hard real-time multi-core testbed comprises Intel Core Duo T2500 processor with dynamic voltage scaling (DVS) capability and runs the Linux Fedora 8 operating system supporting soft real-time scheduling. POSIX threads API and Linux FIFO scheduling policy are utilized to facilitate the design and Dhrystone-based tasks are generated to verify the design. A LabView-based DAQ system is designed to measure the energy consumption of CPU and system board of the testbed. A case study of task allocation and scheduling algorithms is also presented that aim to optimize the schedule feasibility and energy consumed by the processor and memory module in the multi-core platform. The experience from the implementation is summarized to serve as potential guidelines for other researchers and practitioners.     

Energy-Efficient Operation of Water Systems through Optimization of Load Power Reduction in Electricity Markets

Demand response (DR) is gaining more and more importance in the architecture of power systems in a context of flexible loads and high share of intermittent generation. Changes in electricity markets regulation in several countries have recently enabled an effective integration of DR mechanisms in power systems. Through its flexible components (pumps, tanks), drinking water systems are suitable candidates for energy-efficient DR mechanisms. However, these systems are often managed independently of power system operation for both economic and operational reasons. Indeed, a sufficient level of economic viability and water demands risk management are necessary for water utilities to integrate their flexibilities to power system operation. In this paper, we proposed a mathematical model for optimizing pump schedules in water systems while trading DR blocs in a spot power market during peak times. Uncertainties about water demands were considered in the mathematical model allowing to propose power reductions covering the potential risk of real-time water demand forecasting inaccuracy. Numerical results were discussed on a real water system in France, demonstrating both economic and ecological benefits.     

An optimal analytical solution for maximizing expected battery lifetime using the calculus of variations

The exponential growth in the semiconductor industry and hence the increase in chip complexity, has led to more power usage and power density in modern processors. On the other hand, most of today's embedded systems are battery-powered, so the power consumption is one of the most critical criteria in these systems. Dynamic Voltage and Frequency Scaling (DVFS) is known as one of the most effective energy-saving methods. In this paper, we propose the optimal DVFS profile to minimize the energy consumption of a battery-based system with uncertain task execution time under deadline constraints using the Calculus of Variations (CoV). The contribution of this work is to analytically calculate the lower bound of expected battery charge consumption for a given task with uncertain execution time. Most of the research in dynamic voltage and frequency scaling tends to discretize time and value factors. This is presumably because of the context of embedded systems which is mainly based on digital design and algorithms. However, important factors in power and energy, such as supply voltage, supply current, and operational frequency, are continuous functions of time. The CoV is a branch of mathematics, where system parameters are considered as continuous functions of time. So, for dealing with this kind of problems, which system parameters are continuous functions of time, we can use the CoV as a powerful way to solve continuous optimization problems. In this paper, we obtain the exact analytical solution for maximizing battery lifetime, which is applicable to any convex power model.     

Low-energy GALS NoC with FIFO—Monitoring dynamic voltage scaling

In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86 % saturated network achieves 36 % energy-delay product (ED) saving compared to the DVS policy based on link utilization.     

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems

This paper describes a technique for modeling and estimating the power consumptionat the system-level for embedded VLIW (Very Long Instruction Word) architectures.The method is based on a hierarchy of dynamic power estimationengines: from the instruction-level down to the gate/transistor-level. Powermacro-models have been developed for the main components of the system: theVLIW core, the register file, the instruction and data caches. The main goalis to define a system-level simulation framework for the dynamic profilingof the power behavior during the software execution, providing also a break-downof the power contributions due to the single components of the system. Theproposed approach has been applied to the Lx family of scalable embedded VLIWprocessors, jointly designed by STMicroelectronics and HPLabs. Experimentalresults, carried out over a set of benchmarks for embedded multimedia applications,have demonstrated an average accuracy of 5% of the instruction-level estimationengine with respect to the RTL engine, with an average speed-up of four ordersof magnitude.     

Partitioned k-Exclusion Real-Time Locking Protocol Motivated by Multicore Multi-GPU Systems

Graphic processing units (GPUs) have been widely recognized as cost-efficient co-processors with acceptable size, weight, and power consumption. However, adopting GPUs in real-time systems is still challenging, due to the lack in framework for real-time analysis. In order to guarantee real-time requirements while maintaining system utilization in modern heterogeneous systems, such as multicore multi-GPU systems, a novel suspension-based k-exclusion real-time locking protocol and the associated suspension-aware schedulability analysis are proposed. The proposed protocol provides a synchronization framework that enables multiple GPUs to be efficiently integrated in multicore real-time systems. Comparative evaluations show that the proposed methods improve upon the existing work in terms of schedulability.     

Distributed Power Balancing with Linear Prediction and Adaptive On-Off Strategies for CDMA Cellular Mobile Systems

Several distributed balance (DB) power control algorithms that can achieve SIRbalance have already been proposed for cellular mobile systems [1–3].In the present paper, two simple strategies, namely linear prediction andadaptive on-off strategies, are further applied to forward link distributedbalance (DB) power control in DS/CDMA cellular mobile systems. The linearprediction is used to track the variance of the short-term fading andcompensate it in advance, and the adaptive on-off strategy is applied to solvethe problem that the received SIR of all the communication links less than theminimum required SIR. Simulation results indicate that DB power control withthese two strategies can achieve much better performance than the original DBpower control.     

Improving Memory Efficiency of Dynamic Memory Allocators for Real‐Time Embedded Systems

Dynamic memory allocators for real‐time embedded systems need to fulfill three fundamental requirements: bounded worst‐case execution time, fast average execution time, and minimal fragmentation. Since embedded systems generally run continuously during their whole lifetime, fragmentation is one of the most important factors in designing the memory allocator. This paper focuses on minimizing fragmentation while other requirements are still satisfied. To minimize fragmentation, a part of a memory region is segregated by the proposed budgeting method that exploits the memory profile of the given application. The budgeting method can be applied for any existing memory allocators. Experimental results show that the memory efficiency of allocators can be improved by up to 18.85% by using the budgeting method. Its worst‐case execution time is analyzed to be bounded.