40 Gbit/s多路并行光收发模块的研制

基于VCSEL激光器阵列和PIN探测器阵列,设计和制作了40Gbit/s甚短距离的4通道发射4通道接收并行光收发模块.通过高速电路信号仿真设计,解决了信号完整性、串扰和电磁兼容等问题;通过键合金丝长度设计增加了通道带宽.光模块单通道传输速率可达到5 Gbit/s,8通道并行总传输速率达到40Gbit/s,实现了并行光收发模块高速率、高密度、高可靠性以及小体积设计,为甚短距离高速数据处理和传输提供了高可靠的多路数据链接.     

Skew-free parallel optical transmission systems

This paper proposes two kinds of parallel line codes based on multiplexing and nonmultiplexing, and a method of automatic skew suppression based on bit synchronization and frame synchronization. This achieves parallel high-speed optical transmission to overcome bottlenecks in parallel electronic transmission and to increase the distance of high-throughput interconnections. We have developed GaAs coder/decoder large-scale integrations (LSIs) for the coding algorithm and skew suppression, and analog LSIs for compact, low-power, highspeed parallel optical links. Experimental results show that our proposed parallel transmission methods and fabricated LSIs can play a key role in realizing high-speed, long-distance parallel transmission and in reducing the size and power consumption of high-throughput parallel optical links     

30Gbit/s并行光接收模块

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

30Gbit/s Parallel Optical Receiver Module

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

Compact 1.3-um Laser Transmitter for the SL Undersea Lightwave System

The mechanical, optical, and electrical design leading to a reliable, high-performance, robust, and compact transmitter are described. Reliability considerations are of paramount importance in the design of undersea systems. Main features of the laser-fiber-monitor package and the light-feedback control strategy are outlined. The functions of the laser drive circuit, consisting of a low-speed feedback IC and a high-speed modulation IC are discussed. Access to multiple test points through an edge board connector permits automated tuning and reliability testing. The transmitter circuit can provide a 200-mA bias current, about double the expected end of life laser bias requirement, and 60-mA modulation current, double the typical value, with < 0.75-ns rise and fall time. The transmitter operates up to 800 Mbit/s, far beyond the TAT-8 bit rate of 295.6 Mbit/s. Transmitter redundancy is planned to meet the extreme reliability requirements for the transatlantic system. Up to four of the compact transmitters can be mounted per regenerator, thus providing as many as three redundant transmitters for improved system reliability.     

Compact 1.3-µm laser transmitter for the SL undersea lightwave system

The mechanical, optical, and electrical design leading to a reliable, high-performance, robust, and compact transmitter are described. Reliability considerations are of paramount importance in the design of undersea systems. Main features of the laser-fiber-monitor package and the light-feedback control strategy are outlined. The functions of the laser drive circuit, consisting of a low-speed feedback IC and a high-speed modulation IC are discussed. Access to multiple test points through an edge board connector permits automated tuning and reliability testing. The transmitter circuit can provide a 200-mA bias current, about double the expected end of life laser bias requirement, and 60-mA modulation current, double the typical value, with < 0.75-ns rise and fall time. The transmitter operates up to 800 Mbit/s, far beyond the TAT-8 bit rate of 295.6 Mbit/s. Transmitter redundancy is planned to meet the extreme reliability requirements for the transatlantic system. Up to four of the compact transmitters can be mounted per regenerator, thus providing as many as three redundant transmitters for improved system reliability.     

低延迟失真光纤带光缆的研制

研究发现导致12芯光纤带延迟失真的原因有光纤带中各光纤的折射率差、光纤矩阵排列的错位以及光纤中的残余应力，为此开发出一种低延迟失真的新型12芯光纤带，其单模光纤带的延迟失真达0．259ps／m，多模光纤带的延迟失真达0．375ps／m。采用此光纤带研制的288芯骨架槽结构的单模光纤带光缆的延迟失真仅为0．520ps／m。     

Optical self-homodyne DPSK transmission at 1 and 2 Gbit/s over 86 km of fibre

Optical self-homodyne DPSK transmission has been achieved at 1 and 2 Gbit/s data rates with respective receiver sensitivities of ?34.4 dBm and ?32.4 dBm at 10?9 BER. No dispersion penalty was observed after transmission through 86 km of optical fibre with 17 ps/?m/km dispersion at the operating wavelength of 1.53 ?m.     

A 1.5-GHz 130-nm Itanium/sup /spl reg// 2 Processor with 6-MB on-die L3 cache

This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm/sup 2/ die contains 410 M transistors and is implemented in a dual-V/sub t/ process with six Cu interconnect layers and FSG dielectric. The processor runs at 1.5 GHz at 1.3 V and dissipates a maximum of 130 W. This paper reviews circuit design and package details, power delivery, the reliability, availability, and serviceability (RAS) features, design for test (DFT), and design for manufacturability (DFM) features, as well as an overview of the design and verification methodology. The fuse-based clock deskew circuit achieves 24-ps skew across the entire die, while the scan-based skew control further reduces it to 7 ps. The 128-bit front-side bus has a bandwidth of 6.4 GB/s and supports up to four processors on a single bus.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s     

Field demonstration of soliton transmission at 10 Gbit/s over 2000km in Tokyo metropolitan optical loop network

Experimental field transmissions of solitons at 10 Gbit/s over 2000 km have been successfully demonstrated using part of the Tokyo metropolitan optical loop network. The network is composed of conventional dispersion-shifted 200 core optical fibre cable which was not originally intended for soliton transmission. However, with the dispersion-allocated soliton transmission technique, an error-free 13 ps soliton data train was successfully transmitted over 2000 km. The power penalty at a BER of 10^-10 was 3.1 dB     

1D MEMS-based wavelength switching subsystem

Over the past few years, micro-electromechanical systems (MEMS) have emerged as a leading technology for realizing transparent optical switching subsystems. MEMS technology allows high-precision micromechanical components such as micromirrors to be mass produced at low cost. These components can be precisely controlled to provide reliable high-speed switching of optical beams in free space. Additionally, MEMS offers solutions that are scalable in both port (fiber) count and the ability to switch large numbers of wavelengths (> 100) per fiber. To date, most of this interest has focused on two-dimensional and three-dimensional MEMS optical crossconnect architectures. We introduce a wavelength-selective switch based on one-dimensional MEMS technology and discuss its performance, reliability, and superior scaling properties. We also review several important applications for this technology in all-optical networks.     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

InGaAsP/InP 1.3-µm wavelength surface-emitting LED's for high-speed short-haul optical communication systems

Performance and reliability for InGaAsP/InP 1.3-µm wavelength high-speed surface-emitting DH light emitting diodes (LED's) have been investigated. High-speed and high-radiance performances were obtained by the optimal design of both structural parameters and LED driving circuit. Rise and fall times were both 350 ps and peak optical power coupled to a 50-µm core 0.20 NA graded-index fiber at the 100-mA pulse current was - 15.8 dBm with 6-dB optical ON/OFF ratio. A 2-Gbit/s non-return-to-zero (NRZ) pulse transmission over a 500-m span was carried out, Feasibility of using surface-emitting LED's in a high-speed optical communication system has been confirmed. Accelerated aging tests on high-speed LED's were carried out. The half-power lifetimes have been estimated to be more than 1 × 10⁸h at 50°C ambient temperature.     

Electrical characterization of a 500 MHz frequency EBGA package

We developed a high-speed enhanced ball grid array (EBGA) package that can accommodate a 500 MHz ASIC with 15 W of power consumption. This package uses 32 pairs of low voltage differential signals with 400 mV full amplitude and 240 ps risetime as its highest signal speed. The differential signal pairs are designed to run all along with an isometric length including bonding wire, trace, via, and ball in order to cancel out the common mode noise. Adjacent two differential signal pairs are grouped into a channel, which is also designed to have an isometric length. This channel forms a set of parallel transmission paths. The transmission line was formed with characteristic impedance of 60 Ω within a substrate in terms of strip line configuration. This package has a nonstub configuration using electroless nickel and gold plating. The ground pad is connected to the ground plane through the sidewall of the cavity, which is the nearest path in order to reduce ground inductance-per-pin down to 12-24 pH. Time domain waveform was simulated at the frequency of 500 MHz as the electrical characteristics of this package. The time domain waveform in an actual package was measured at risetime of 120 and 240 ps, which corresponds to 500 and 800 MHz of frequency, respectively. The simulated waveform correlates very well with the measured waveform. Signal integrity was excellent, which had small overshoot-undershoot and crosstalk noise less than 10%. Differential skew and channel skew were minimized to less than 10 ps to achieve a parallel transmission. We confirmed this at system level using our package with a 500 MHz ASIC. With our package we are able to accommodate an 800 MHz ASIC based on the time domain waveform results     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

A high-capacity broadband packet switch architecture based on a multilink approach

Broadband packet networks based on asynchronous transfer mode (ATM) are expected to provide a wide range of services, including motion video, voice, data and image. When these networks become prevalent, some applications such as motion video and high-speed LAN interconnections will place a very large bit rate requirement on the channels. Currently, the physical layer supported by the synchronous optical network (SONET) allows the transmission of up to 2.4 Gbit/s with the OC-48 optical interface. However, it is not feasible for the electronic packet switch to route packets at this rate on a single link. In this paper we present a design of a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the lower link rate, which can be at 150 Mbit/s, while having the ability to support a virtual circuit at a higher rate (up to 2.4 Gbit/s). The main contribution of the design is that packet sequence on a channel is still maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain. Analytical results show the performance advantages of multilink design with respect to delay, throughput and packet loss probability.     

Radio-Over-Fiber 16-QAM, 100-km Transmission at 5 Gb/s Using DSB-SC Transmitter and Remote Heterodyne Detection

By using a double-sideband suppressed carrier (DSB-SC) optical transmitter and a remote self-heterodyned (RSH) detection method, we experimentally and analytically proved the feasibility of a radio-over-fiber system using a 16-QAM signal at 5 Gb/s and 18 GHz, with a transmission distance of 100 km between a mobile service center and a base station. The transmission system performance was carefully analyzed by considering optical amplifier noise, fiber nonlinearity, phase noise, frequency response, and analog-to-digital converter (ADC) quantization noise. The 18-GHz, 16-QAM signal can be radiated from the base station to a remote antenna port without any upconverter, and the remote antenna port consists of a downconverter and high-speed digital signal processors (DSPs) to recover the 16-QAM signal. The high-speed DSP, which partially compensates the intersymbol-interference (ISI) and phase-noise-induced system penalties, was enabled by 20-Gs/s ADCs. The algorithms used in the DSP blocks were also described in details.     

具有连续自动温度补偿功能的10Gb/s光收发模块

设计并制作了一种10Gb/s光收发模块,在宽温度范围内能够保持稳定的光功率和消光比。基于背电流和光功率的换算比例,计算其偏置电流修正值和调制电流修正值,实现了光模块运行过程中激光器的工作参数可自动连续调节。通过高速电路信号仿真设计,解决了信号完整性、串扰和电磁兼容等问题。光模块收发通道可以独立工作,传输速率可达10Gb/s,实现了光模块高速率、高稳定性以及小体积设计,为甚短距离高速数据传输和处理提供了高可靠性的数据链接。     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²