A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2-μm-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well     

10-Gb/s millimeter-wave signal generation using photodiode bias modulation

We present a simple 120-GHz-band millimeter-wave (MMW) modulation method that uses the bias-voltage dependence of unitraveling-carrier-photodiode output power, which we call photodiode (PD) bias modulation. We investigated the dependence of the output-power-saturation mechanisms on the bias voltage. We used a lowpass filter in the bias circuit to increase the modulation bandwidth, and the 3-dB modulation bandwidth was over 7 GHz. We demonstrated the modulation of 120-GHz MMW signals at a data rate of 10 Gb/s using PD bias modulation.     

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design     

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

A 10-Gb/s silicon bipolar IC for PRBS testing

A 10 Gb/s silicon bipolar IC for pseudorandom binary sequence (PRBS) testing was fabricated and tested. The IC features PRBS generation of the sequences of length 2¹⁵-1 and 2²³-1 b up to 10 Gb/s according to CCITT recommendations. Furthermore, the IC is capable of analyzing PRB sequences of the same length and generation polynomials so that a full test of components is possible. In addition, a new PRBS test word synchronization can be provided between two chips for external multiplexing of the sequences up to 40 Gb/s. The IC can be connected to a standard PC, so evaluation of the error test data can be performed in a flexible way. The IC was fabricated with the HP25 process of Hewlett Packard company, the chip size is 32 mm², and it consumes 6.2 W at the nominal supply voltage of -5 V     

40-Gb/s high-power modulator driver IC for lightwave communicationsystems

A monolithic integrated modulator driver with a data decision function for high-speed optical fiber links is presented. The integrated circuit (IC) was manufactured in a 0.2-μm gate length AlGaAs/InGaAs high electron mobility transistor technology with an f_T of 68 GHz. The modulator driver IC features differential configuration and operates up to 40 Gb/s with a clock phase margin of 210° and an output voltage swing of 2.9 V_p-p at each output. The maximum slew rate of the output signal is 200 mV/ps. The power dissipation of the circuit is 1.6 W using a single supply voltage of -5 V     

Top surface-emitting vertical-cavity laser diodes for 10-Gb/s data transmission

Intensity modulated proton-implanted top surface-emitting vertical-cavity InGaAs QW lasers (VCSELs) with a small-signal modulation bandwidth of 12 GHz butt-coupled to multimode fibers are investigated as light source for optical interconnection. At 10-Gb/s pseudorandom data rates the bit-error rate (BER) remains under 10/sup -11/ after transmission over 500 m of graded index multimode fiber. Optimum transmission behavior is achieved for linearly polarized nearly single-mode laser operation with a side-mode suppression of better than 25 dB under modulation. Spectral characterization indicates that linearly polarized single-mode light output is essential for good BER performance.     

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.     

A 20-Gb/s silicon bipolar 1:4-demultiplexer IC

This paper presents a 20-Gb/s 1:4-demultiplexer for future fiber-optic transmission systems. It uses an 0.4-μm emitter double polysilicon 21-GHz f_T Si bipolar foundry process. This is the highest data rate of a 1:4-DEMUX reported so far in any technology. The 1:4-DEMUX features a tree-type architecture with one frequency divider and a channel switch circuit. The circuit design was carefully optimized to achieve high speed and moderate power dissipation. It consumes 1.4 W with a single -4.5-V supply     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

A fully integrated SiGe receiver IC for 10-Gb/s data rate

A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2 ⁷-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5×4.5 mm2 and consumes 4.5 W from -5 V     

80-Gb/s Low-Driving-Voltage InP DQPSK Modulator With an n-p-i-n Structure

We present a traveling-wave-electrode InP-based differential quadrature phase-shift keying modulator with a novel n-p-i-n waveguide structure. The structure features low electrical and optical propagation losses, which allow the modulator to operate at a high bit rate together with a low driving voltage and a low insertion loss. We successfully demonstrate 80-Gb/s modulation with a driving voltage of only 3 $hbox{V}_{rm pp}$ in a push–pull configuration. The chip size is just 7.5 mm$, times ,$ 1.3 mm.      

An AlGaAs/InGaAs pseudomorphic HEMT modulator driver IC with lowpower dissipation for 10-Gb/s optical transmission systems

An optical modulator driver integrated circuit (IC) has been developed for 10-Gb/s optical communication systems. To achieve both high-frequency (HF) operation and low power dissipation, 0.2-μm T-shaped gate AlGaAs/InGaAs pseudomorphic high electron-mobility transistors (HEMTs) have been employed for their large transconductance g_m of 610 mS/mm and high cutoff frequency f_T of 67.5 GHz. In addition, optimizing input logic swing, switching transistor size in the output driver, and using cascode-current mirror circuits with small output conductance enable power dissipation as low as 1 W to be achieved at a 10-Gb/s nonreturn-to-zero (NRZ) signal output with 3 V_p._p. This is the lowest value ever reported for power dissipation. As an additional function, the output-voltage swing can be controlled in the range from 2 to 3.3 V_p._p. by the current mirror circuit for the purpose of adjusting the optical-output-signal duty factor through an optical modulator     

WDM PON using 10-Gb/s DPSK downstream and re-modulated 10-Gb/s OOK upstream based on SOA

A signal remodulation scheme of 10-Gb/s differential phase-shift keying(DPSK) downstream and 10-Gb/s on-off keying(OOK) upstream using a semiconductor optical amplifier(SOA) and a Mach-Zehnder intensity modulator(MZ-IM) at the optical networking unit(ONU) side for wavelength division multiplexed passive optical network(WDM PON) is proposed.Simulation results indicate that error-free operation can be achieved in a 20-km transmission,and the receiver sensitivity of return-to-zero differential phase-shift keying(RZ-DPSK) is higher than nonreturn-to-zero differential phase-shift keying(NRZ-DPSK) in the proposed scheme.     

Demonstration of a Bidirectional 80-km-Reach DWDM-PON With 8-Gb/s Capacity

A bidirectional 80-km-reach 64-channel dense wavelength-division-multiplexing passive optical network with 50-GHz channel spacing based on wavelength-locked Fabry-Peacuterot laser diodes is demonstrated. By changing the position of the broadband light source (BLS) for the upstream channels to the remote node, both the need for a high-power BLS and the power penalties induced by backscattering are overcome. Packet-loss-free transmission is obtained, guaranteeing 125 Mb/s per channel (8-Gb/s capacity in a single direction) without the support of an optical amplifier     

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.     

A 10-Gb/s laser/modulator driver IC with a dual-mode activelymatched output buffer

A laser/modulator driver IC for 10-Gb/s-SONET OC-192-fiber optic transmitters is described. Depending on the user application, the IC is capable of driving more than 100 mA of current into a laser diode or over 50 mA into an electro-absorption or Mach-Zehnder modulator. Rise and fall times below 20 pS are achieved. The driver employs a novel dual-mode actively matched output buffer that provides a dc-coupled back termination of either 25 or 50 Ω. Compared to an output buffer with a resistive termination, this buffer dissipates only half as much power. In addition, the buffer has the the ability to reject external bias and will therefore not load bias sources used to set laser threshold currents and modulator offset voltages. The low power consumption makes the IC most suitable for co-packaging with uncooled lasers and electro-absorption modulators. The driver is fabricated in a 0.25-μm gate length production GaAs PHEMT process with substrate thru vias, thin-film resistors, and MIM capacitors