Performance comparison of high-order IFLF and LF linear phase lowpass OTA-C filters with and without gain boost

Design and performance comparison of high-order operational transconductance amplifier and capacitor (OTA-C) filters using leapfrog (LF) and inverse-follow-the-leader-feedback (IFLF) structures are investigated. The filters are designed for a 125 MHz seventh-order equiripple group delay lowpass characteristic with and without gain boost and simulated in 0.25 μm 2-V CMOS. A fully differential highly linear OTA with cross-coupled input pairs and regulated cascode output is used for the simulation. Simulated results show that while the IFLF OTA-C filter can achieve a higher gain boost, the LF OTA-C filter has better other performances.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

On design of a novel class of selective CIC FIR filter functions with improved response

The Cascaded-Integrator-Comb (CIC) filter is a non-recursive (FIR) filter which is multiplier free, consisting only of two building blocks (simple integrator stage and simple comb filter stage) and has a linear phase. This paper summarizes some key points of classical CIC filters and proposes a novel class of CIC FIR filter functions. A novel class of CIC filter functions maintains simplicity of FIR filters by avoiding the multipliers, but shows excellent performances in term of insertion loss in stopband and selectivity with respect to conventional CIC filters. A set of simulations along with illustrative examples is conducted in order to compare the attenuation characteristics of the classical CIC filter functions and the proposed novel class of selective CIC FIR filter functions. For the same level of a constant group delay τ = 45.5 s, a classical CIC filter function has insertion loss of 166.3 dB, and designed novel filter function has a higher level of insertion loss 206.55 dB.     

Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-Q Switched-Capacitor Filters

The periodical nonuniform individual sampling scheme has been shown suitable for capacitance spread and total capacitor area reduction in high quality (Q) factor switched-capacitor (SC) filters. However, the use of periodical nonuniform clock signals results in additional aliasing components in the output spectrum. This paper presents a simple model to analyze the generation of such alias components and gives practical expressions to estimate their power. The results are verified through circuit simulation of a 10.7-MHz second-order SC bandpass filter in a 0.35-mum CMOS technology. Implications on the use of this technique in the design of intermediate-frequency filters are discussed     

Using a Genetic Algorithm to Optimize Capacitance Ratio Approximations in SC Filters

Accurate capacitance matching is one of the main design issues in switched-capacitor (SC) filters. Using identical unit capacitors in parallel to implement each filter capacitor, combined with a careful layout design, can provide an accuracy of 0.1% in the filter coefficients. The disadvantage of this technique is the fact that it can be directly applied only if the coefficients can be expressed as ratios of integer numbers. As a result, coefficient approximations are required, leading to frequency response errors. In this paper, a genetic algorithm (GA) is used to find the optimum capacitance ratio approximations by rational numbers that minimize the total number of unit capacitors for a given error tolerance in the frequency response. Design examples in 0.35 μm CMOS are presented and simulated to illustrate the proposed approach and verify its effectiveness.     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

A Reconfigurable Channel Filter for Software Defined Radio Using RNS

This paper presents a high-speed FIR channel filter using residue number system (RNS) whose frequency response can be reconfigured to adapt to a multitude of channel filtering specifications of a multi-standard software defined radio (SDR) receiver. The channel filters in the channelizer of an SDR extract multiple narrowband channels corresponding to different communication standards from the wideband input signal. The proposed architecture has been synthesized on TSMC 0.18 μm CMOS standard cell technology. Synthesis result shows that the proposed reconfigurable FIR channel filter, for a Digital Advanced Mobile Phone Systems (D-AMPS) example, offers speed improvement of 42% and AT complexity reduction of 26% over existing reconfigurable FIR method.     

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit ΔΣ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm² chip fabricated in 0.5-μ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback     

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.     

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.     

Low-distortion switched-capacitor filter design techniques

The distortion mechanism in switched-capacitor (SC) filters are considered, and closed-form expression relating switched-capacitors filter distortion to circuit parameters are derived. Design techniques for low-distortion applications are discussed and are applied to a sixth-order experimental filter. The filter design uses a fully differential class A/B op amp with a continuous-time common-mode feedback circuit. Distortion measurements show that for 82-dB dynamic range (relative to noise floor) the total harmonic distortion of 0.02% within the whole 4-kHz bandwidth and 0.07% within 20-kHz bandwidth.     

多通带低群延迟误差FIR滤波器设计的迭代算法

常数低群延迟有限冲击响应（FIR）滤波器在通信等领域得到了广泛应用,尤其是要求无波形失真、信号延迟小的场合。而低群延迟的FIR滤波器,其相位响应只能做到近似线性相位,其群延迟只能做到近似常数。为了减小与期望常数群延迟之间的误差,最近提出的通过迭代更新相位误差上界函数来逐步减小群延迟误差的方法,只考虑了单通带滤波器的minimax设计。本文将把该方法推广至多通带FIR滤波器的minimax设计和约束最小二乘设计,先对各通带单独处理使每个通带的最大群延迟误差有效降低后,再考虑各通带之间平衡,对各子带的最大群延迟误差进行折中,进而使整个通带上的最大群延迟误差继续减小。对约束最小二乘设计还特别考虑了通过修改收敛参数来解决相位误差约束过紧时设计问题无解的问题。仿真实例表明,该方法能有效减小多通带滤波器的最大群延迟误差。      

Series/Parallel Time-Multiplexed Switched-Capacitor Filters with Programmability Based on Non-Uniform Sampling

This paper presents an improved scheme for programmable time-multiplexed (TM) switched-capacitor (SC) filters. The proposed approach uses a novel sampling technique, which eliminates the need for resolution/area tradeoffs. The programmability of each processing channel is based on the use of non-uniform clock signals with noise-shaped sampling energy. No capacitor values are modified for programming frequency response parameters and, hence, the performance of the TM SC filter is not sacrificed for programmability. Such a sampling technique not only leads to an accurate frequency response control, but also allows the design procedures and the resulting SC circuit implementation to be simplified. A test-chip including a programmable second-order TM SC filter with a multiplexing order of four, which operates in series or in parallel mode, was fabricated in conventional CMOS technology. Measurement results demonstrate the effectiveness and versatility of the proposed technique.     

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision     

High-Selectivity Switched-Capacitor Bandpass Filter with Quasi-Continuous Quality Factor Tunability

This paper describes the design and implementation of a second-order switched-capacitor (SC) bandpass (BP) filter with very wide quality factor (Q) programmability range. The filter selectivity is digitally programmed by varying the effective sampling frequency of an SC branch, without modifying any capacitor value. The proposed approach allows a quasi-continuous Q-factor tunability avoiding, in principle, the inherent quantization error associated to any traditional programming technique. Automatic Q-factor tuning is performed by using a scheme based on an amplitude-locking loop approach. Experimental results obtained from a 0.8-m CMOS integrated prototype demonstrate the versatility of the proposed technique for high-Q SC BP filters.     

Continuous-time integrated FIR filters at microwave frequencies

We discuss adaptive integrated finite-impulse response (FIR) filters operating in the continuous time domain. These filters become attractive to implement at microwave frequencies. An important topological property of the traveling wave FIR filter is presented, and its advantages when used as an adaptive equalizer are pointed out. Design considerations and modeling aspects of compact on-chip delay lines are given. Simulation results for an adaptive equalizer operating at a data rate of 10 Gb/s are presented.     

Microelectronic switched capacitor filters

An explanation of what switched-capacitor (SC) filters are and how they work is given. Attention is focused on low-sensitivity SC filters, which can be developed from a general passive ladder where the branches are arbitrary impedances. The equations that describe the filter components are reviewed, and the characteristics of these low-sensitivity filters are outlined. Applications of the filters in telecommunications are discussed     

An approximation algorithm to improve capacitance matching in the design of SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. However, this procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of unit capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios causing acceptable errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure was applied in the design of a sixth-order SC band-pass filter, which has been fabricated in a 0.35 μm CMOS technology. The fabricated filter occupies an area of 0.913 mm², exhibits low sensitivity to fabrication process deviations and has an output dynamic range of 79.2 dB.     

Switched-capacitor filters driven with very low voltage clock signals

It is well known that the switches of a very low voltage (1.5V) switched-capacitor filter in a standard CMOS process must be driven with a clock signal higher than the power supply, often generated on-chip. The authors present, however, a technique to implement very low voltage switched-capacitor filters with switches driven at the same very low voltages.<>