Preparation of atomically flat surfaces on silicon carbide using hydrogen etching

Hydrogen etching of 6H- and 4H-SiC(0001) surfaces is studied. The as-polished substrates contain a large number of scratches arising from the polishing process which are eliminated by hydrogen etching. Etching is carried out in a flow of hydrogen gas at atmospheric pressure and temperatures around 1600–1700°C attained on a tantalum strip heater. Post-etching atomic force microscopy images show periodic arrays of atomically flat terraces that are a few thousand angstroms wide. These terraces are separated by steps 15 Å high in the 〈1 $ < 1\bar 100 > $ 00〉 directions. Often, the surface is seen to be faceted with steps on neighboring facets forming 60° angles and offset in the c-direction by half a unit cell. Images of incompletely etched surfaces show early stages of etching where one can see remnants of surface damage in the form of arrays of hexagonal pits. On the larger scale, the surface has a hill-and-valley type morphology. The observed features are interpreted in a model based on the symmetry of the SiC unit cell and crystal miscut.     

Effects of substrate surface preparation on chemical vapor deposition growth of 4H-SiC epitaxial layers

The effects of chemical mechanical polish (CMP) and pre-growth oxidation and etching of vicinal 4H−SiC substrates on the quality of epitaxial films have been investigated. Samples with and without a collodial silica CMP and oxidation/etch treatment were studied with optical microscopy, cross section transmission electron microscopy (TEM) and atomic force microscopy (AFM) before and after chemical vapor deposition. Evidence of polishing damage was evident prior to growth in all samples without CMP treatment. Oxidation and etching appeared to generate defects by preferential etching of bulk defects such as dislocations and low angle grain boundaries. Evidence of the polishing damage remained after chemical vapor deposition (CVD) growth on the samples without CMP and the defect density was worse for the oxidized samples compared to the unoxidized ones. The unoxidized CMP wafer had the lowest defect density and rms roughness of the samples studied.     

Effects of process parameter variations on the removal rate in chemical mechanical polishing of 4H-SiC

The effects of temperature, slurry pH, applied pressure, and polishing rotation rate on the material removal rate during chemical mechanical polishing (CMP) of 4H-silicon carbide wafers using colloidal silica slurry and polyurethane/polyester fiber polishing pads have been studied. Measured removal rates varied from around 100 Å/hr to nearly 2500 Å/hr depending on the values of the various parameters. The amount of material removed was determined by measuring the wafer mass before and after polishing. Variations in temperature and slurry pH did not produce significant changes in the measured removal rates. Higher polishing pressures resulted in increased material removal rates from 200 to 500 Å/hr but also produced excessive polishing pad damage. Variations in pad rotational speeds produced the largest changes in material removal rates, from around 200 to around 2000 Å/hr for rotational speeds between 60 and 180 rpm, but the variations were non-linear and somewhat inconsistent. This CMP formula is shown to consistently produce damage free surfaces but the optimum removal rate is slow.     

Final polishing of Ga-polar GaN substrates using reactive ion etching

Reactive ion etching of {0001} oriented plate-like GaN single crystals has been investigated using SiCl₄:Ar:SF₆ chemistry. The reactive ion etching process is highly chemical. Large anisotropy of the etching rate and of the morphology has been established on (000 ) N-polar and (0001) Ga-polar sides of the GaN crystals, with remarkably higher rate on the N-polar side. Atomic force microscopy measurements have shown smooth surface and good polishing effect obtained on Ga-polar side, while N-polar surface exhibits an increased roughness of a factor of 10 after RIE.     

High-quality conformal silicon oxide films prepared by multi-step sputtering PECVD and chemical mechanical polishing

High-quality conformal oxide films were obtained by using multi-step sputtering (MSSP) plasma enhanced chemical vapor deposition (PECVD) process with argon ion sputtering and chemical mechanical polishing (CMP). The repeated deposition by plasma enhanced chemical vapor deposition (PECVD) and anisotropic etching of oxide films by multi-step sputtering PECVD improve the step coverage and gap filling capability significantly. The argon plasma treatment enhances the binding energy of Si-O in the SiO₂ network, and the temperature dependence of stress for MSSP oxide film showed no hysteresis after the heating cycle up to 440 °C. The stress-temperature slope of MSSP oxide film was found to be much less than that of conventional PECVD oxide film. The slope for 1.1 μm thick film is about 5.8×10⁵ dynes/cm²/°C which is smaller than that of thermally grown oxide film. It seems that MSSP oxide film reduces stress-temperature hysteresis and becomes more dense and void-free in the narrow gaps with inter-metal spacing of 0.5 μm. After filling of the narrow gap, we adopted the CMP process for global planarization and obtained good planarization performance. The uniformity of the film thickness was about 4% and the degree of the planarization was over 95% after CMP process.     

Progress in silicon carbide semiconductor electronics technology

Silicon carbide’s demonstrated ability to function under extreme high-temperature, high-power, and/or high-radiation conditions is expected to enable significant enhancements to a far-ranging variety of applications and systems. However, improvements in crystal growth and device fabrication processes are needed before SiC-based devices and circuits can be scaled-up and incorporated into electronic systems. This paper surveys the present status of SiC-based semiconductor electronics and identifies areas where technological maturation is needed. The prospects for resolving these obstacles are discussed. Recent achievements include the monolithic realization of SiC integrated circuit operational amplifiers and digital logic circuits, as well as significant improvements to epitaxial and bulk crystal growth processes that impact the viability of this rapidly emerging technology.     

Electrical characteristics of rectifying polycrystalline silicon/silicon carbide heterojunctions

This paper presents a study of the rectifying properties of heavily doped polycrystalline silicon (polysilicon) on 4H silicon carbide (4H-SiC). Current properties and barrier heights were found using analysis of the heterojunction. This revealed that Schottky analysis would be valid for the large barrier height devices. Isotype and an-isotype devices were fabricated on both p-type and n-type SiC and the electrical characteristics were investigated using capacitance vs voltage measurements, current vs voltage measurements (I-V), and temperature I-V measurements. Extraction of the barrier height, built-in potential, and Richardson constant were made and then compared to theoretical values for the heterojunction. Temperature I-V measurements demonstrated that the current transport mechanism is thermionic emission, confirming the validity of the Schottky diode model. The I-V characteristics show near ideal diode rectifying behavior and the capacitance-voltage characteristics show ideal junction space charge modulation for all polysilicon/SiC combinations. These experimental results match well with heterojunction band-offset estimated barrier heights and demonstrate that the barrier height of the polysilicon/4H SiC interface may be controlled by varying the polysilicon doping type.     

Chemical mechanical polishing of freestanding GaN substrates

Chemical mechanical polishing (CMP) has been used to produce smooth and scratch-free surfaces for GaN. In the aqueous solution of KOH, GaN is subjected to etching. At the same time, all surface irregularities, including etch pyramids, roughness after mechanical polishing and so on will be removed by a polishing pad. The experiments had been performed under the condition of different abrasive particle sizes of the polishing pad. Also the polishing results for different polishing times are analyzed, and chemical mechanical polishing resulted in an average root mean square (RMS) surface roughness of 0.565 nm, as measured by atomic force microscopy.     

SiLK dielectric planarization by chemical mechanical polishing

As the feature size of integrated circuits is driven to smaller dimensions the importance of the inter- and intralayer isolator capacitance in future metallization schemes becomes more pronounced. Organic polymers with low dielectric constants are one class of material choice for the replacement of SiO₂. However, their successful integration into functional circuits requires new fabrication procedures. The embedded dielectric scheme offers an evolutionary path for their successful integration into a subtractive etched, aluminum-based integrated circuit. This scheme can effectively lower the total capacitance while minimally changing the rest of the metallization fabrication process. However, the non-conformal deposition of spin-on polymers requires an effective planarization process. Therefore, this paper focuses on the planarization capability of a chemical mechanical polishing process (CMP) using SiLK resin as the interlayer dielectric material. The experimental results demonstrate the high planarization capability of the CMP process using a commercially available slurry. The post-CMP degree of planarization is greater than 95% for all feature dimensions and this planarity can be achieved rapidly. SiLK dielectric coatings are therefore considered as a promising candidate to replace SiO₂ in existing Al/W-based technologies.     

GaN自支撑衬底的化学机械抛光研究

Chemical mechanical polishing （CMP） has been used to produce smooth and scratch-free surfaces for GaN. In the aqueous solution of KOH, GaN is subjected to etching. At the same time, all surface irregularities, including etch pyramids, roughness after mechanical polishing and so on will be removed by a polishing pad. The experiments had been performed under the condition of different abrasive particle sizes of the polishing pad. Also the polishing results for different polishing times are analyzed, and chemical mechanical polishing resulted in an average root mean square （RMS） surface roughness of 0.565 nm, as measured by atomic force microscopy.     

Electrochemical polishing of monocrystalline silicon with specific crystallographic planes

In this study, an electrolytic polishing experimental system was developed to obtain a uniform, flat-surfaced monocrystalline silicon with specific crystallographic planes. Several key factors reflecting specific electrolytic polishing on monocrystalline silicon with specific crystallographic planes were summarized. These factors, including electrolyte, conduction mode, Schottky barrier, semiconductor body resistance, and unidirectional conductivity, were analyzed comprehensively through energy spectrum analysis, theoretical modeling, and potential simulation. The effects of electrolytic polishing process were obtained, and corresponding solutions were proposed. Finally, the electrolytic polishing experiment for monocrystalline silicon with specific crystallographic planes was conducted. A uniform, flat-surfaced monocrystalline silicon with no metamorphic layer was then obtained. The flatness error of the center area was less than 0.201 µm. Furthermore, the crystallographic planes of monocrystalline silicon wafers showed no change.     

Surface morphology of silicon carbide epitaxial films

Silicon carbide (SiC) semiconductor technology has been advancing rapidly, but there are numerous crystal growth problems that need to be solved before SiC can reach its full potential. Among these problems is a need for an improvement in the surface morphology of epitaxial films that are grown to produce device structures. Because of advantageous electrical properties, SiC development is shifting from the 6H to the 4H polytype. In this study of both 6H and 4H-SiC epilayers, atomic force microscopy and other techniques were used to characterize SiC epilayer surface morphology. Observed features included isolated growth pits a few micrometers in size in both polytypes and triangles (in 4H only) approximately 50 um in size for epilayers 3 um in thickness. Also observed in some epilayers were large steps with heights greater than 20 nm. We found that there are significant differences between the morphology of 6H and 4H epilayers grown under identical conditions. We were able to improve surface morphology by avoiding conditions that lead to excess silicon during the initial startup of the growth process. However, the observed morphological defect density in both 6H and 4H epilayers was still the order of 10⁴ cm^-2 and varied widely from run to run. As expected, we found that morphological defects in the SiC substrates play a role in the formation of some epilayer surface features.     

碳化硅材料在微电子机械系统中的应用

碳化硅材料包括单晶碳化硅、多晶碳化硅、无定形碳化硅等,由于其显著的材料特性,如耐热、耐磨、化学惰性和高硬度等,近年来在微电子机械系统(MEMS)领域受到越来越多的关注。应用特定的工艺条件将碳化硅材料制成MEMS器件,可以在某些特殊条件下使用,克服了常规材料本身的局限性,从而为碳化硅材料的应用开发了新的领域。追踪这一国际热点研究问题,针对以上几种不同形态材料,分别举例说明了它们在MEMS领域应用的进展情况。     

Prediction of sawing force for single-crystal silicon carbide with fixed abrasive diamond wire saw

Fixed abrasive diamond wire saw has been used to cut hard-and-brittle materials into wafers, such as silicon carbide. The force of a single abrasive determines the cutting depth, and affects material removal mode and crack propagation length. Therefore, the sawing force is a key factor that affects the surface/subsurface quality of wafers. In this paper, a numerical sawing force predicting method considering wire saw parameters was proposed with the combination of both ductile removal and brittle fracture removal for each single abrasive. A new calculation method of single abrasive cutting force considering frictional force component and new material removal way considering the effect of lateral crack were adopted. Then the influences of process parameters and wire parameters on sawing force were analyzed. Finally, mathematical sawing force formulas described by both process parameters and wire saw parameters were obtained using the new sawing force prediction method. The validity of this prediction method and sawing force formulas was verified through experiments in the literature under the same process parameters and wire saw parameters.     

Laser doping of silicon carbide substrates

A direct-write laser conversion technique was used to produce n-type and p-type doped tracks on SiC substrates. Polycrystalline and single-crystal SiC substrates were investigated. The tracks irradiated in an inert gas exhibit a higher electrical resistance than those generated in dopant-containing atmospheres. The effects of various processing parameters, such as the laser-matter interaction time, laser-beam characteristics, number of exposures to the laser beam, and ambient gas in the laser processing chamber, are examined. The laser conversion technique can be used for selective-area doping of silicon carbide substrates to build semiconductor devices for high-temperature applications.     

Effect of organic acids on copper chemical mechanical polishing

In chemical mechanical polishing (CMP) of Cu, organic acids are often used as additives of slurries. This paper studied the effects of citric acid, oxalic acid, glycolic acid and glycine on Cu CMP performance. Our experiments explored the difference of these organic acids in surface reactions with Cu. The results showed that organic acids could chelate the passive film of Cu, and oxalic acid would further form precipitates with copper ions to change the chemical and mechanical action during CMP. Potential-pH diagrams, electrochemical polarization and impedance analyses were used to examine the behaviors of Cu in various organic acid slurries. The results indicated that the proposed equivalent circuits from impedance analysis for Cu CMP system could provide a good index to surface roughness. Furthermore, we also discussed the effects of used organic acids on reducing particle contamination after Cu CMP by measuring the difference of isoelectric points between Cu and α-Al₂O₃. The result showed that the addition of organic acid could efficiently decrease particle contamination.     

Auger electron spectroscopy study of reactive ion etched silicon carbide

Reactive ion etching (RIE) of bulk 4H-SiC based on CHF₃-O₂ plasma was studied by varying the rf power and process pressure. The elements on the etched surface and the surface roughness were characterized by Auger electron spectroscopy and atomic force microscopy, respectively. It was found that the surface roughening is mainly caused by Al contamination and C rich layer (C residues) induced micromasking effect. The micromasking effect is in turn determined by the dc self-bias developed at the substrates. A threshold dc self-bias exists at around −320 to −330 V, beyond which no micromasking effect was observed. This observation is explained in terms of physical ion bombardment and sputtering in the RIE process.     

High field activation of micropipes in high resistivity silicon carbide

Micropipes in high resistivity (p≥5 kΩcm) SiC are highly activated in parallel electric fields (vertical devices) at room temperature starting at very low fields of 5-10 kV/cm, especially in the doped material. No activation of micropipes is observed in high fields (>100 kV/cm) perpendicular to their orientation (lateral devices). In the last case, the high field limitation is due to surface flashover phenomena taking place at 100-175 kV/cm in vacuum ambient and depending strongly on the material growth technology and the gap length. Non-ohmic behavior was not observed in lateral devices up to high applied fields. The high field characterization method is proposed as a powerful tool for the evaluation of the quality of SiC material for next-generation high voltage/high power devices.     

Atomic scale engineering of nanostructures at silicon carbide surfaces

The atomic scale ordering and properties of cubic silicon carbide surfaces are investigated by room and high-temperature scanning tunneling microscopy. In this review, we will focus on the Si-terminated β-SiC(100) surfaces only. Self-formation of Si atomic lines and dimer vacancy chains on the β-SiC(100) surface is taking place at the phase transition between the 3×2 (Si-rich) and c(4×2) surface reconstructions. Using a rigorous protocol in surface preparation, it is possible to build very long, very straight and defect free Si atomic lines, forming a very large superlattice of massively parallel lines. These self-organized atomic lines are driven by stress. They have unprecedented characteristics with the highest thermal stability ever achieved for nanostructures on a surface (900 °C) and the longest atomic lines ever built on a surface (micrometer scale long). Investigating their dynamics, we learn that their dismantling at high-temperature results from collective and individual mechanisms including one-by-one dimer removal. Overall, this is a model system especially suitable for nanophysics and nanotechnologies.     

A novel method for etching trenches in silicon carbide

In this paper, a novel trench etching technique for silicon carbide is described. In this technique, ion implantation is used to first create an amorphous silicon carbide region. The amorphous layer is then etched away by wet chemical etching. Trenches of 0.3 to 0.8 μ have been obtained using a single implantaion/etching step. It has been demonstrated that deeper trenches can be obtained by repeating the implantation/etching step with platinum as a masking material. The etched surface was found to be smooth when compared with reactive ion etched surfaces reported for silicon carbide.