A framework for design and testing of analog integrated circuits

A global methodology for analog and mixed analog-to-digital VLSI design requires close interaction between simulations, CAD tools, measurements, and testing. An integrated hardware and software environment (framework) that implements this methodology in a systematic way is described. As an example of its application, the modeling of errors in multistage analog-to-digital converters (ADCs) is described. The framework has a unique software organization designed to facilitate the interpretation of measurement results and the feedback of information to the design world. The perfectly modular nature of the software makes it easy to gain a fundamental understanding of error mechanisms. In the ADC example, this understanding eliminates the need to probe internal parts of a circuit since information on internal errors can be recovered from external measurements     

ESD in integrated circuits

A review of the effects of electrostatic discharge (ESD) on semiconductor integrated circuits is presented. The principles of the human body model (HBM), the machine model (MM) and the charged device model (CDM) test methods are outlined, and their relative merits and drawbacks are discussed. Techniques, such as the transmission line pulse method, which may be used to characterise ESD protection circuit elements are also presented. The concept of ESD protection circuit designs and some typical ESD protection circuit elements are presented. The main design and process parameters are identified, and the main categories of damage under ESD conditions are shown. Models of the behaviour of the protection circuit elements under high current conditions are presented, and the boundary conditions for damage are discussed. The issues that will influence ESD protection circuit behaviour in the future are discussed.     

Gallium arsenide digital integrated circuits

The motivations behind the development of GaAs integrated circuits (IC) are two-fold: to integrate high speed logic with optical sources and to meet the increasing demand of realising LSI/VLSI with higher speed and lower power dissipation for large scale computer applications. GaAs gigabit circuits have been growing in complexity to more than 3000 gates on a single chip. Although this is encouraging, more efforts are needed to improve production yield. By far the most work on GaAs digital IC has been done using MESFET as the active devices. MOSFET technology is yet to mature from the practical IC point of view. The logic gate types used in circuits are predominantly of the enhancement-mode driver and depletion-mode load configuration (E/D). A brief survey of the state-of-the-art of GaAs digital IC is presented. Implemented circuits are described and compared with those achieved through various technologies. GaAs gate arrays, multipliers, accumulators and memories are discussed. At liquid N₂-temperature, a switching time of 5·8 ps/gate has been achieved for 0·35μm gate devices. This and similar other results lead to the conclusion that at the VLSI level of future Gbit circuits, GaAs devices in the form of HEMT operated at 77 K can outperform Si-devices. At′ LSI complexities, experimental GaAs MESFET and 300 K HEMT have a lead on Sicircuits—it is then this range in which Gbit/GaAs should find their application.     

Building blocks for integrated graphene circuits

The observation of single sheets of graphite (graphene) presents new possibilities for carbon-based nanoelectronics. We report defect tolerant configurations for a nearly reflectionless 120 degrees turn and nearly reflectionless symmetric and asymmetric splitters, which can be cut from graphene. Connections between zigzag strips of different widths can be made with either low or high reflectance depending on the connection shape.     

Thin diamond films for integrated circuits

We propose a technology for the synthesis of thin diamond films, which allows integrated emission elements of the vacuum triode type to be created on a substrate surface. The process includes three main stages: (i) deposition of a thin diamond film onto a silicon substrate; (ii) lithographic procedure with an aluminum mask; and (iii) post-growth in a regime ensuring required emission properties. An emission triode design is presented that can be realized using the proposed technology.     

Flexible high-performance carbon nanotube integrated circuits

Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 μm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm(2) V(-1) s(-1) and an on/off ratio of 6 × 10(6). We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques.     

Aluminum alloying in silicon integrated circuits

The metallization step in the fabrication of silicons devices and integrated circuits requires the alloying of silicon to aluminium to create ohmic contacts in the window regions. This heat treatment often results “spearing” which, especially in integrated circuits, represents a significant failure mode. The topology and kinetics of the spearing process are discussed and evidence is presented which tendsto suggest a liquid phase reaction between silicon and aluminium. A variety of metallization techniques, involving aluminium, by which it is believed spearing can be prevented are also discussed.     

The test needs of application-specific integrated circuits

This paper discusses the particular test needs of non-standard, application-specific integrated circuits (ASICs). It covers the need for accurate device simulation integrated with a post-processor and test system software, to enable cost-effective testing to be performed.     

Four-dimensional microscopy of defects in integrated circuits

We demonstrate four-dimensional microscopy of defects in integrated circuits by a technique that combines laser-scanning confocal reflectance microscopy with one-photon optical-beam-induced current (1P-OBIC) imaging. Accurate information is obtained about the three-dimensional structure of the defect and the kind of material (metal, semiconductor, or dielectric) that is damaged by the defect. The same focused probe beam simultaneously produces the 1P-OBIC and reflectance signals from the illuminated sample spot. The hardware development cost is minimal for a laser-scanning confocal microscope, and the image reconstruction procedure is computationally efficient. Imaging is demonstrated on defects that are caused by electrical overstress and unwanted generation centers. Exclusive three-dimensional distributions of the semiconductor and metal sites in the integrated circuit reveal defect features that are difficult to recognize with confocal or 1P-OBIC imaging alone.     

Backgating in GaAs devices and integrated circuits

This paper reviews current understanding of backgating in GaAs integrated circuits and discusses approaches used to predict and mitigate its effect. Current theoretical approaches to explain backgating are reviewed and the impact of materials, process techniques, and design on backgating are also discussed. A standard backgating test structure and test proposed at the 1990 GaAs IC Symposium are described.     

Reliability of plastic-encapsulated integrated circuits in moisture environments

An overview of the factors affecting the reliability of plastic-encapsulated ICs in moisture environments is presented. Particular attention is given to the moisture-related failure mechanism EMA (electrolytic metal attack). The package design and process steps and techniques developed at RCA (through identification of the proper analytical models, thorough engineering programs, and by the statistical design of experiments) are detailed. Particular attention was paid to eliminating chlorides and their sources. The nature and state of ongoing plastic-package moisture-resistance programmes and future expectations are described.     

Electromigration in submicron interconnect features of integrated circuits

Electromigration (EM) is a complex multiphysics problem including electrical, thermal, and mechanical aspects. Since the first work on EM was published in 1907, extensive studies on EM have been conducted theoretically, experimentally, and by means of computer simulation. Today EM is the most significant threat for interconnect reliability in high performance integrated circuits.Over years, physicists, material scientists, and engineers have dealt with the EM problem developing different strategies to reduce EM risk and methods for prediction of EM life time. During the same time a significant amount of work has been carried out on fundamentally understanding of EM physics, of the influence of material and geometrical properties on EM, and of the interconnect operating conditions on EM. In parallel to the theoretical studies, a large amount of work has been performed in experimental studies, mostly motivated by urgent and specific problem settings which engineers encounter during their daily work. On the basis of accelerated electromigration tests, various time-to-failure estimation methods with Blacks equation and statistics have been developed. The big question is, however, the usefulness of this work, since most contributions about electromigration and the accompanying stress effects are based on a very simplified picture of electromigration.The intention of this review paper is to present the most important aspects of theoretical and experimental EM investigations together with a brief history of the development of the main concepts and methods. We present an overview of EM models from their origins in classical materials science methods up to the most recent developments for submicron interconnect features, as well as the application of ab initio and first principle methods. The main findings of experimental studies, important for any model development and application, will also be presented.     

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.     

Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications

A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.