MOSFET的电离辐照效应

本文研究了MOSFET的电离辐照效应,给出了辐照在MOSFET栅介质中引起氧化物电荷对阈电压的贡献与辐照剂量和栅偏置电场的相互依赖关系.结果表明,辐照引起的氧化物电荷与管子的沟道种类无关.另外,漏源电压对MOSFET的辐照响应也有影响.统计数据表明,对管子阈电压漂移有贡献的界面态的能级范围大约为 E_s/2.对实验结果进行了讨论.     

MOSFET的低温(77°K)电离辐照特性

本文采用MOSFET的亚阈外推测量技术,研究MOSFET在低温(77°K),~(60)Coγ射线辐照下,辐照感生氧化层电荷和界面态。在77°K辐照下,n沟道MOSFET辐照感生氧化层电荷比室温更加明显。77°K时,辐照感生界面态的增加是室温辐照下的20％左右。p沟MOSFET在77°K辐照下,处于截止偏置的退化大于导通偏置。导通偏置辐照时,未观察到界面态的产生。     

MOS器件~(90)Sr-~(90)Y源电离辐射效应研究

介绍了利用90Sr-90Y源辐照装置对MOSFET进行低剂量率辐射条件下的电离辐射效应实验,着重研究了MOSFET的辐照敏感参数随辐照剂量的变化规律,并对实验结果进行了分析讨论。     

MOSFET的热载流子损伤及其退火

对国内常规54HC工艺制作的PMOSFET进行了F-N热载流子注入损伤实验,研究了MOSFET跨导、阈电压等参数随热载流子注入的退化规律,特别是从微观氧化物电荷和界面态变化对阈电压影响角度,对国内外较少见报道的MOSFET热载流子损伤在室温和高温(100°C)下的退火特性进行了研究,并从该角度探讨了MOSFET热载流子注入产生氧化物电荷和界面态的特性。     

集电极偏置电流对硅npn晶体管γ辐照效应的影响

对硅npn双极晶体管(C2060)室温下不同集电极偏置电流条件下γ辐照的总剂量效应进行了研究.结果表明,npn晶体管的辐照损伤程度随着辐照总剂量的增加而增加;尤其是实验中发现:在相同的辐照总剂量下随着辐照时集电极偏置电流的增加,晶体管的辐照损伤程度却在减轻.空间电荷模型的观点并不能很好地解释辐照损伤与辐照集电极偏置电流的关系.文章对空间电荷模型进行了修正,认为除氧化物俘获电荷和界面俘获电荷外,还会在外基区Si-SiO2界面附近形成电中性的电偶极子.利用修正后的理论可以很好地解释所有的实验结果.     

集电极偏置电流对硅npn晶体管γ辐照效应的影响

对硅npn双极晶体管(C2060)室温下不同集电极偏置电流条件下γ辐照的总剂量效应进行了研究.结果表明,npn晶体管的辐照损伤程度随着辐照总剂量的增加而增加;尤其是实验中发现:在相同的辐照总剂量下随着辐照时集电极偏置电流的增加,晶体管的辐照损伤程度却在减轻.空间电荷模型的观点并不能很好地解释辐照损伤与辐照集电极偏置电流的关系.文章对空间电荷模型进行了修正,认为除氧化物俘获电荷和界面俘获电荷外,还会在外基区Si-SiO2界面附近形成电中性的电偶极子.利用修正后的理论可以很好地解释所有的实验结果.     

一种新的辐射试验技术--低能X射线辐照

首先分析了辐照条件下MOSFET氧化层及Si／SiO2界面陷阱电荷和界面态电荷产生的机理,随后介绍了一种低能X射线辐射系统,最后讨论了X射线辐照后nMOSFET阈值电压的变化。结果表明采用X射线辐照对nMOSFET的阈值电压的影响与^60Co辐照影响的规律一致。     

PDSOI CMOS SRAM单元临界电荷的确定

PDSOI CMOS SRAM单元的临界电荷(Critical Charge)是判断SRAM单元发生单粒子翻转效应的依据.利用针对1.2μm抗辐照工艺提取的PDSOI MOSFET模型参数,通过HSPICE对SRAM 6T存储单元的临界电荷进行了模拟,指出了电源电压及SOI MOEFET寄生三极管静态增益β对存储单元临界电荷的影响,并提出了在对PDSOI CMOS SRAM进行单粒子辐照实验中,电源电压的最恶劣偏置状态应为电路的最高工作电压.     

短沟道MOSFET中的电离辐照效应模型

用一种电荷层方法模拟了离化辐照对短沟道MOSFET的影响。离化辐照的主要效应是引入了氧化层捕获电荷(OTC)和界面捕获电荷(ITC)。应用二维电荷层模型,研究了沟道长度在4.65μm和0.27μm之间的晶体管。用±4.0×10~(11)cm~(-2)的净OTC和ITC值范围,相应于10~6拉德左右的剂量(SiO_2)来研究总的剂量效应。ITC和OTC对每一个工作区都有显著的影响。在亚阈值区内,漏电流对这些电荷的灵敏度为指数关系。更现实的模型必须包括ITC电荷的能量分布以及二维电荷分配效应。在三极管区内,ITC和OTC的影响与二维电荷分配效应不能区别。这就意味着短沟道MOSFET阈值电压偏移的简单分析不能提供二维效应与辐照感应效应的物理区别。在饱和区内,合成的OTC和ITC有助于场电荷成为沟道电荷,这种沟道电荷可以改变沟道夹断区边缘的临场点。对于短沟道晶体管来说,这种临界场效应改变了输出特性“弯曲”区的形状,而且会改变饱和区的输出导电性。     

全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

MOSFET中大幅度随机电报信号噪声的动力学特性

对 MOSFET器件的随机电报信号噪声 ( RTS)的特征进行了研究。室温下在极细沟道样品中观测到了大幅度 (大于 60 % )的 RTS,通过测量 RTS的俘获时间和发射时间与栅压和温度的依赖关系 ,获得了氧化层陷阱的位置与能级 ,证实了氧化层陷阱的热激活模型在细沟道 n MOSFET中仍然成立。同时发现当器件工作在弱反型区时 ,RTS幅度基本与栅压无关。对 RTS的动力学机制的分析及数值模拟表明 ,当沟道宽度减小至 4 0 nm以下时 ,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对 RTS的幅度的影响起主导作用。     

非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型.通过Pao-Sah积分得到了漏电流的表达式.该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到.结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数.对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

A 2-D analytical threshold voltage model for fully-depleted SOIMOSFETs with Halos or pockets

The exact solution of the two-dimensional (2-D) Poisson's equation has been analytically derived for fully-depleted (FD) SOI MOSFETs with Halos or pockets. The approach uses a three-zone Green's function solution technique. Explicit equations for the 2-D electrical potential as well as for both front- and back-side threshold voltages have been derived. The accuracy of the equations has been verified by a 2-D numerical device simulator. From the presented results, it can be concluded that the analytically derived model for the electric potential and threshold voltages are in good agreement with 2-D numerical simulation data     

A quasi-3D analytical threshold voltage model of small geometry MOSFETs

Numerical 2D and 3D models of MOSFETs, which have been developed so far, are accurate but take enormous computer time and memory for their implementation. It restricts their use only to the design and development of submicron devices. A computationally faster, analytical quasi-3D model for the threshold voltage of small geometry MOSFETs, which should be useful for VLSI circuit simulation, has been presented in this paper. The model is based on a rigorous 2D analytical model. An equivalence between the analytical 2D model and the Yau's charge sharing model has been established, and the same has been utilized to incorporate the narrow width effect. The important features of the present work are: (1) realistic channel implantation profiles for nMOSFETs have been used in developing the 2D model; (ii) the effect of birds' beaks on the lateral confinement of charges in the channels of oxide isolated MOSFETs has been considered in a simple manner; and (iii) the fringing of electric field near the edges of channels (widths) has also been considered empirically. The simulated values of the threshold voltages exhibiting 2D and 3D effects compare well with those obtained using a numerical 3D simulator (MICROMOS) and with available experimental data. The model is also capable of predicting the inverse narrow width effect observed in MOSFETs with fully recessed field oxide.     

COMPUTER AIDED ANALYSIS OF CARRIER ENERGY TRANSPORT IN MOSFETs

The two-dimensional numerical simulation of energy transport for MOSFETs ispresented,in which the effect of generation,recombination and temperature gradient of carrierson the characteristics of devices are considered.An improved mobility model is also proposed.The numerical results of micron and submicron MOSFETs show that the present model fitsexperiment very well.     

Nonquasistatic transient model of fully-depleted SOI MOSFET and itsapplication to the analysis of charge sharing in an analog switch

A fast one-dimensional (1-D) numerical model suitable for circuit analysis has been developed for fully-depleted silicon-on-insulator MOSFETs. The novel important feature of our CAD-oriented approach consists in a rigorous treatment of the nonquasistatic charge redistribution that ensures accuracy under fast switching conditions. The capabilities of this model are exemplified through the simulation of an analog transmission gate to evaluate the impact of charge sharing effects     

Threshold voltage model for MOSFETs with high-k gate dielectrics

An analytic threshold voltage model, which can account for the short channel effect and the fringing field effect of sub-100 nm high-k gate dielectric MOSFETs, has been developed. The model considers the two-dimensional (2D) effect both in silicon bulk and in gate dielectric layer. The results of the model are consistent with 2D numerical simulation results     

Generalized saturation analysis for submicron MOSFETs and MODFETs

This paper presents a comprehensive generalized saturation analysis for submicron MOSFETs and MODFETs. An analytical expression for the saturation voltage of submicron MOSFETs is proposed. The dependence of the saturation voltage of short-channel MOSFETs on both the gate voltage and the channel length has been extensively studied. A comparison is made among conventional, numerical and proposed saturation voltages. The proposed model is acceptable as compared with the numerical data. Similar observations of the saturation-voltage dependence on both the gate voltage and the channel length have been obtained for MODFETs. These obtained similarities between MODFETs and MOSFETs suggest that the analysis is applicable to all field effect transistors where a conducting channel is created between a source region and a drain region.     

Body effect in tri- and pi-gate SOI MOSFETs

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate.     

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI.