Proton isolation for GaAs integrated circuits

Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively biased ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO2field oxide and a three-layered dielectric-Au mask which is definable to 3-µm linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 10⁶h at 290°C, is not a lifetime limiting component in a GaAs IC process.     

Proton Isolation for GaAs Integrated Circuits

Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively based ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO/sub 2/ field oxide layer and a three-layered dielectric- Au mask which is definable to 3-µm linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 10/sup 5/ h at 290° C, is not a lifetime limiting component in a GaAs IC process.     

Use of implant isolation for fabrication of vertical cavity surface-emitting laser diodes

The authors report the first successful use of implant isolation by singly charged oxygen to fabricate MBE-grown GaAs-AlGaAs vertical cavity surface-emitting lasers (VCSELs). Almost identical room-temperature pulsed thresholds of 26 mA on 15 mu m diameter devices with 0.25 mu m GaAs active thicknesses were obtained using implant isolation against etched mesa isolation. The planar nature of implant isolation greatly simplifies processing to allow more sophisticated use of VCSELs.<>     

GaAs质子注入及其在微波器件中的应用

本文报导了用质子注入GaAs形成高阻隔离层的实验研究及其在微波半导体器件方面的应用.并对其隔离机理和隔离层的热稳定性问题作了讨论,指出质子注入GaAs制作隔离层是一项可靠的技术.     

质子注入对GaAs基器件隔离研究

质子注入参数对注入型垂直腔面发射激光器（Vertical cavity surface emitting laser, VCSEL）的电流限制孔径位置及电流限制效果具有较大影响。文中从质子注入的能量和剂量及其相互作用对VCSEL电流限制孔径的影响规律及机制出发,通过理论模拟分析了注入参数对质子分布及注入区电阻值的影响。在此基础上,采用VCSEL外延片进行了质子注入实验研究。实验结果和理论分析均表明:注入区电流隔离效果及质子分布受注入能量和剂量共同调控。当注入参数为320 keV、8×1014 cm?2时,经430 ℃、30 s退火后可得到结深约0.7 μm,平均射程距有源区约1.3 μm,电阻值达4.6×107 Ω?cm2的质子注入区。使用该参数制备的VCSEL器件实现了较好的激光激射,证明该质子分布不仅可避免VCSEL有源区损伤,而且能实现较好的电流隔离效果,满足VCSEL电流限制孔径的制备要求。研究结果对质子注入型VCSEL的芯片结构及工艺优化具有重要指导意义。     

A novel self-aligned isolation process for VLSI

We have developed a novel NMOS process for VLSI isolation. The process employs an RIE of the field oxide followed by a metal liftoff and a high-energy boron sheet implant. The energy of the implant and the metal thickness are selected such that the boron penetrates the field oxide, but not the metal. Performing the isolation doping after growing the field oxide eliminates encroachment of the isolation doping into the channel end while simultaneously providing a self-aligned channel stop. The doping concentration in the channel region is determined by implants that are independent of the doping concentration in the channel stop area. With this technique, we have obtained excellent device performance as well as rigorous device isolation. Even at the isolation spacing of 0.7 µm, there was <1-pA leakage at 5 V. The active devices exhibit minimal body effect coefficients (0.1-0.2), good subthreshold behavior (80 mV/DEC), and low junction capacitance. The experimental data is confirmed by two-dimensional analysis.     

1/4-µm CMOS isolation technique using selective epitaxy

A new CMOS isolation technique has been developed for reducing isolation width to a 1/4 µm with large latchup immunity. This technique is supported by three key processes. The first is to form 1/4 µm thick insulator films on trench sidewalls, which are shaped perpendicularly to the substrate surface plane. The second is to refill the trenches with selectively grown single-crystal silicon with a planar surface. The third is to form a low-resistance well for latchup prevention. The CMOS devices are composed of n-channel devices fabricated on a p-type substrate and p-channel devices fabricated on an n-type epi-layer. In this isolation structure, a parasitic MIS operation with vertical channel induces large leakage currents along the isolation sidewalls. However, the highly doped p-type region, due to deep boron implant in the p-type substrate, is effective to suppress parasitic operation. Submicrometer-gate CMOS inverter operation is shown, when the channel stop implant is carried out.     

Ion implantation and rapid thermal processing of Ill-V nitrides

Ion implantation doping and isolation coupled with rapid thermal annealing has played a critical role in the realization of high performance photonic and electronic devices in all mature semiconductor material systems. This is also expected to be the case for the binary III-V nitrides (InN, GaN, and A1N) and their alloys as the epitaxial material quality improves and more advanced device structures are fabricated. In this article, we review the recent developments in implant doping and isolation along with rapid thermal annealing of GaN and the In-containing ternary alloys InGaN and InAlN. In particular, the successful n- and p-type doping of GaN by ion implantation of Si and Mg+P, respectively, and subsequent high temperature rapid thermal anneals in excess of 1000°C is reviewed. In the area of implant isolation, N-implantation has been shown to compensate both n- and p-type GaN, N-, and O-implantation effectively compensates InAlN, and InGaN shows limited compensation with either N- or F-implantation. The effects of rapid thermal annealing on unimplanted material are also presented.     

Method of creating local semi-insulating regions on silicon wafersfor device isolation and realization of high-Q inductors

Penetrating proton beams from a compact ion cyclotron (diameter: 1.5 m, height: 2 m) were employed to create local semi-insulating regions within silicon substrates to facilitate device isolation in mixed-mode (analog-digital) integrated circuits (IC's) and realization of RF IC's with high-Q inductors. Experiments revealed that resistivity values of I MΩ-cm could be reached by practical proton fluences on silicon wafers of original resistivity of more than about 1 Ω-cm. Significant improvement was evidenced on Q values of irradiated inductors. Effect of reduced inductor metal conductivity from bombardment was over-shadowed by the more enhanced Q behavior, if the proton fluence is sufficiently large     

Improved CMOS field isolation using germanium/boron implantation

A novel germanium/boron implantation technique for improving the electrical field isolation of high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40% with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits     

New self-aligned planar resonant-tunneling diodes for monolithiccircuits

Resonant-tunneling diodes (RTDs) with a new planar configuration have been fabricated with a new self-aligned process that is compatible with that of silicon integrated-circuits technology. The size of the RTD is determined by a shallow boron implant, and the individual RTDs are isolated by a deep proton implant. There is no deep mesa etch. Because of the self-alignment nature of the process, the peak current and voltage of the RTDs are highly uniform. The mean of the standard deviation of the peak current for 4-μm² RTDs is 2.3% and the smallest RTDs fabricated are less than 1 μm²     

A new self-aligned VLSI Isolation process using thin-metal lift-off

A new Self-Aligned Isolation process using thin-metal Lift-off (SAIL) has been developed for NMOS VLSI circuits. In this process, a field oxide is grown first, followed by a channel-stop implant that is self-aligned to the active area. The self-alignment is achieved through a lift-off process that utilizes only thin metal. The self-alignment of channel-stop implant to active area is shown to improve the breakdown voltage of MOSFET devices. Direct window isolation is used to eliminate oxide encroachment and reduce outdiffusion of boron channel-stop implant into the active area. As a result, the narrow width effect is minimal. Since thin-metal lift-off can be performed reproducibly with high yield, this makes SAIL a viable process for VLSI fabrication.     

Electron transport in implant isolation GaAs layers

We report results of ac electrical characterisation of diode structures with Hg electrodes and an implant isolation layer formed on a n⁺GaAs substrate. The C–f and G–f characteristics at varying bias voltage between 0 and 10 V at room temperature were examined. The frequency of 50 mV measuring signal was changed from 100 Hz to 10 MHz. The implant isolation layers were performed by ion implantation of oxygen with 100 keV followed by 250 keV process on well conducting commercial GaAs substrate. Ion doses ranging from 10¹² to 5×10¹³ cm⁻² were used. The high frequency C–V characteristics showed that all tested implant isolation layers were fully depleted beginning from zero bias voltage. The G–f characteristics showed that ac conductance increases as a function of frequency and approximately follows ω^s dependence with s=0.6–0.9. These results are consistently interpreted as the result of the transport of injected carriers through the implant isolation layer via a hopping mechanism involving defects. Only in the samples with low level of defect density (low ion dose of 10¹² cm⁻²) for low frequency from 100 Hz to 5 kHz the high level conductance does not depend on frequency. This can be interpreted as the result of the transport of injected carriers through the extended states in conduction band.     

Rapid isothermal processing for fabrication of GaAs-basedelectronic devices [HBTs]

The use of rapid isothermal processing (RIP) is detailed for each of the three annealing steps in the fabrication of heterostructure-based devices such as heterojunction bipolar transistors (HBTs). RIP can be used for the alloying of ohmic metal contacts, annealing of ion-bombarded regions for device isolation or parasitic capacitance reduction, and for conventional implant activation annealing. High-speed (f_T=65 GHz) HBTs were achieved using RIP for all of the required heating steps. The authors compare the use of several types of silicon carbide-coated graphite susceptors for eliminating slip formation on 2- and 3-in-diameter GaAs wafers during high-temperature implant activation annealing     

Deuteron bombardment of gallium arsenide for device isolation

Multiple energy bombardments of n+ GaAs with deuterons have shown that much lower doses are needed for carrier removal than with proton bombardment. At equivalent doses, deuteron bombardment induced high resistivity is more thermally stable. Thus GaAs device isolation with deuteron bombardment has various significant advantages over current methods.     

Proton implantation isolation for microwave monolithic circuits

We show that proton implantation isolation effectively reduces RF losses for microwave monolithic integrated circuits and that the degree of effectiveness is a function of the induced damage depth. RF losses are mostly due to the current conduction in semiconducting active or buffer layer.     

Proton implanted singlemode holey vertical-cavity surface-emitting lasers

Wedge-shaped holes have been fabricated in the top mirror of proton implant confined vertical-cavity surface-emitting lasers. The index confinement and selective loss introduced by these patterns improved the performance by both increasing the singlemode power and reducing the threshold current of the lasers. A maximum single fundamental mode power of 3.5 mW with a simultaneous reduction of lasing threshold compared to an unmodified laser was observed. Multimode operation was suppressed over the entire laser operating range.     

Sidegating characteristics as a function of distance and dose forimplanted and metallic sidegates on proton-isolated GaAs

Sidegating characteristics have been measured on MESFETs as a function of sidegate distances ranging from 3 to 570 μm and proton isolation doses ranging from 0 to 5×10¹⁴ atoms/cm² . In addition, the composition of the sidegate is shown to be a significant factor in modulating saturated transistor current     

Proton isolation of Si δ-doped GaAs

The use of proton isolation to define Si δ-doped GaAs device structures is reported and was found to be effective in defining δ-doped layers with a two-dimensional electron density of up to 6.8×10¹² cm^-2. Qualitatively the electron transport characteristics of the proton-isolated devices were identical to those of equivalent mesa-etched devices     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.