Anadigm更新现场可编程模拟阵列

Anadigm公司推出了第二代现场可编程模拟阵列(FPAA) AN2 2 0 E0 4 ,属于其 Anadigmvortex产品范畴 ,该产品系列也结合了一套 EDA工具、可变模拟模块和可编程硅技术。与第一代 FPAA产品相比 ,它具有动态定义和实时控制性能 ,可对模拟功能进行升级和控制。AN2 2 0 E0 4应用于信号调节、过滤、数据获取和闭合环路控制时 ,可作为分立部件和模拟 ASIC/ASSP器件的替代方案。AN2 2 0 E0 4采用 44引脚 QFP封装 ,现已提供样品和量产业务。Anadigm更新现场可编程模拟阵列…     

现场可编程滤波器阵列单元

通过对通用数字滤波器公式的细致分析，建立了一种最为精简实用的滤波器模块单元，给出了模拟结果，进而提出了编程滤波器阵列单元的概念，提供了在实用数字滤波的具体实现中比数字信号处理（ＤＳＰ）更直接，更高效的途径。     

开关电容现场可编程模拟阵列FPAA的频域SPICE仿真

根据C.F．KURTH和G．S.MOSCHYTZ的采用z域四口等效电路对开关电容网络进行双口分析的理论,以现场可编程模拟阵列FPAA实现的PID控制器为例,建立用于频域仿真的SPICE模型,从而方便地用SPICE软件对PID校正后的整个控制系统的稳定性进行仿真分析。     

开关电容器现场可编程模拟阵列的频域SPICE仿真

根据C．F．KURTH和G．S．MOSCHYTZ采用z域四口等效电路对开关电容器网络进行双口分析的理论。以现场可编程模拟阵列实现的PID控制器为例，建立了一个用于频域仿真的SPICE模型。从而方便地用SPICE软件对PID校正后整个控制系统的稳定性进行仿真分析。     

一种双模式的CMOS现场可编程模拟阵列的分析与设计

本篇文章提出了基于采用高度灵活的互连盒的互连网络的一种新型的现场可编程模拟阵列(FPAA)结构,该结构可以在双模式下工作包括离散时间模式和连续时间模式,以追求在不同应用场合下的性能要求。高度灵活的互连盒中的开关不仅用来作为可编程开关还直接作为开关电容中电荷转移的开关来使用,大大减少了离散时间模式下信号路径上的开关,提高了整体电路的性能。该款FPAA采用0.18um CMOS工艺,3.3V电源电压。后仿结果显示互连网络的最大带宽可达265MHz, 从示例的测试结果可以看出该款FPAA在连续时间模式下可工作在2MHz信号带宽下,无杂散动态范围可达54dB, 离散时间工作模式下的处理精度可达96.4%。     

现场可编程模拟阵列的微处理器配置模式及接口方法

现场可编程模拟阵列AN10E40加上直观性软件AnadigmDesigner,给数字和模拟电路设计者提供了设计模拟电路的便利条件,可以在AN10E40上快速设计精确、无漂移、具有温度补偿及可编程的模拟电路.AN10E40有两种装载配置SRAM的工作模式:模式0是微处理器引导模式,模式1是串行ROM引导模式.文中介绍了现场可编程模拟阵列AN10E40的微处理器配置模式,给出了AN10E40与51系列单片机的接口方法及程序设计.     

基于现场可编程模拟阵列FPAA的音频均衡器设计

 数字音频均衡器中最关键的部分就是滤波系统,滤波系统精度的高低、效果的好坏直接决定着整台均衡器对音频的修饰效果.本文采用开关电容技术的现场可编程模拟阵列FPAA构成的数字音频均衡器,选择了一种全新构建音频均衡器的设计方法,以求获得一个使用方便、音效调节效果好、成本低的音频均衡器系统.开关电容椭圆函数滤波器的整体频率响应特性与标准曲线比较接近,是一种较好的音频均衡器滤波器系统.随着开关电容技术、电流模和电压模技术的进一步发展,FPAA可广泛用于工控、医疗、仪器、高级音频、自动测试设备、汽车、通信等领域.     

FPAA的音频滤波器设计实例

基于开关电容的现场可编程模拟阵列(FPAA)是最近发展起来的新的模拟技术。以AN221E04芯片为切入点介绍了FPAA的硬件结构及其相应的EDA软件AnadigmDesigner2。给出一个应用实例并阐明了FPAA的一般设计方法。     

MPAA020现场可编程模拟阵列

ＭＰＡＡ０２０是Ｍｏｔｏｒｏｌａ公司新推出的可编程模拟ＡＳＩＣ,该 在似于常用的ＦＰＧＡ〉它以ＳＲＡＭ编程数据,由基于开关电容技术的模拟单元阵列组成,主要用于各种模拟信号的放大、滤波和转换,本文介绍了ＭＰＡＡ０２０芯片的基本结构、主要性能参数、相应的开发软件及其在模拟电子系统设计中的应用。     

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

In this work a strategy for testing analog networks, known as Transient Response Analysis Method, is applied to test the Configurable Analog Blocks (CABs) of Field Programmable Analog Arrays (FPAAs). In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Two FPAAs from different manufacturers and distinct architectures are considered as CUT. For one of the devices there is no detailed information about its structural implementation. For this reason, a functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted, and then, the relationship between these parameters and CAB component deviations is investigated. The other considered device allows a structural programming in which the designer can directly modify the values of programmable components. This way, faults can be injected by modifying the values of these components in order to emulate a defective behavior. Therefore, it is possible to estimate the fault coverage and test application time of the proposed functional test method when applied to both considered devices.

A Current Conveyor based Field Programmable Analog Array

An approach for designing a Field Programmable Analog Array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An Analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. Analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

FPGA器件设计技术发展综述

现场可编程门阵列(Field Programmable Gate Array,FPGA)作为一种可编程逻辑器件,在短短二十多年里从电子设计的外围器件逐渐演变为数字系统的核心,在计算机硬件、通信、航空航天和汽车电子等诸多领域有着广泛的应用。伴随着半导体工艺技术的进步,FPGA器件的设计技术取得了飞跃性突破。该文在回顾FPGA发展历史的同时,对目前主流FPGA器件的前沿技术进行总结,并对新一代FPGA的发展前景进行展望。     

基于可编程跨导运算放大器POTA低通有源滤波器设计

该文给出了基于可编程跨导运算放大器(POTA)的有源滤波器设计方法,能在一定范围内实现跨导值程控调节, 提高调节精度和准确度。并且利用Jacobi法求解相似对角形矩阵,避免解高次方程的难题。所设计的有源滤波电路不易受分布电容的影响,稳定性好、灵敏度低。本文给出了设计实例,显示了该方法的优点。     

基于DSP FPGA GPP-CPU的软件无线电信号处理平台的硬件设计

DSP FPGA构成的数字硬件系统以其强通用性、灵活性、高处理速度而使其在诸多领域有广泛的应用;GPP(General Purpose Processor)功能强大,不仅可以做复杂的控制算法,还具有强大的数字信号处理能力。本文介绍了一种基于DSP FPGA GPP-CPU的软件无线电信号处理通用硬件平台的设计。