一种相位准确度高幅值失配度低的正交LO驱动电路

提出了一种工作在1.1～1.2GHz的相位准确度高、幅值失配度低的正交LO驱动电路.它主要由高频放大器、二阶的无源多项滤波器、相位和幅度校准电路(PMCC)组成.PMCC是一种利用前馈技术实现的低功耗电路,大大提高了正交信号的正交性,降低了相邻支路信号的幅值误差.仿真结果表明,经过PMCC校准后,输出正交信号的相位误差可以降低大约一半,而幅度误差可以降低到原来的十分之一.PMCC可直接驱动混频器,无需额外的驱动电路.本设计已经用TSMC 0.25μm CMOS工艺实现并进行了验证.测试结果表明本文提出的校准电路能够获得高正交性(＜2°)和低幅值误差(＜0.1%)的正交信号,测试的最大功率增益为5.25dB,在2.5V的电源电压下,消耗的电流约为6mA,芯片面积为1.0mm×1.0mm.     

An auto-I/Q calibrated CMOS transceiver for 802.11g

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1/spl deg/ and gain mismatch to 0.1dB. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point.     

ADAPTIVE CALIBRATION OF I AND Q MISMATCH IN QUADRATURE RECEIVER

The mismatch of in-phase and quadrature channels in quadrature receiver affects and constrains radar detection performance in coherent radar.It is necessary to keep the in-phase and quadrature branches symmetrical.In this letter,an adaptive method to detect imbalance parameters is derived by means of evaluating channel errors from the received signal sequences.No matter how the bias degree of the gain and phase errors in I/Q channels are ,the proposed adaptive scheme can obtain good calibration results.And the required calculations are only a few multiplications and additions.No need of a special test signal,the introduced method is simple to implement and easy to operate.     

一种新型宽带接收机I/Q通道失配的数字校正方法

由于各种因素的影响,I/Q通道之间通常会发生失配现象,这会降低接收机的动态范围,进而影响接收机的性能。本文提出了一种宽带接收机中L/Q幅相误差校正的数字方法：首先通过一种时域方法以获得误差信息,籍此计算校正所需参数,再由Newton插值多项式构造滤波器组对I/Q信号进行滤波校正。仿真表明,这种数字校正方法能有效地提高宽带接收机I/Q通道的正交一致性。     

Effect of Phase Mismatch on Image Rejection in Weaver Architecture

In a radio frequency receiver, image signals degrade the sensitivity of the receiver for receiving desired signals. This letter analyzes the effect of phase mismatch on image rejection in the Weaver architecture, which has been proposed to reject image signals. Weaver architecture requires the phase difference between the I signal and Q signal of the first and second local oscillators (LOs) to be 90deg. However, the realization of accurate 90deg phase shifters is very difficult. It is found here that an accurate 90deg phase shifter is not essential in Weaver architecture. Instead, by making the phase mismatch between the I and Q signals of the first LO be equal to that of the second LO, image rejection can be performed, being insensitive to the phase mismatch. The reason for this is mathematically analyzed and simulation results are presented     

一种应用于WLAN相位可调的本振缓冲器

该文提出了一种应用于WLAN相位可调的本振缓冲器,用于校准直接下变频收发机的I/Q两路不平衡。该电路通过开关输入MOS管源极的电容阵列,延迟本振信号,从而调节信号的相位。该文采用SMIC 0.18m工艺实现了4.8~6GHz的I/Q两路本振缓冲器的设计,其版图面积为650550m2。仿真结果表明,在5位控制字作用下,I或者Q路本振缓冲器的相移在0~8的范围内呈现近乎线性的变化,而本振缓冲器的输出功率的变化范围只有0.2dB。     

宽带数字接收机I/Q幅相不一致性的校正

随着数字技术的发展,正交双通道变换在接收机中得到了广泛的应用。但是,由于各种因素的影响,I／Q通道的正交一致性并不能得到完全的保证,这会降低接收机的动态范围,进而影响接收机的性能。本文提出了一种宽带数字接收机I／Q幅相不一致性的校正方法,首先通过一种时域方法获得误差信息,接着构造滤波器组对I／Q信号进行校正。仿真结果表明,这种方法能有效提高宽带接收机I／Q通道的正交一致性。     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

A 75-dB image rejection IF-input quadrature-sampling SC /spl Sigma//spl Delta/ Modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 200-kHz signal bandwidth.     

正交调制器的校准设计

在当前许多复杂调制射频信号源中,随着数字基带信号越来越多的加入．需要正交凋制器将其调制到需要的载波信号上。正交调制器原理简单：将生成好的I/Q两路基带信号调制到两路正交的载波上,合路后输出。但是在实现时,想获得好的指标就需要考虑载波相位误差,I/Q基带信号幅度不平衡以及载波泄漏等问题。文章给出了一种正交调制器的校准方案,可以减少和模拟以上三种现象造成的调制误差,并给出自动校准和手动校准两种方法。     

Frequency-Selective I/Q Mismatch Calibration of Wideband Direct-Conversion Transmitters

The current trend in building low-cost yet flexible radio transceivers is to use the so-called direct-conversion principle, which is based on complex (I/Q) up- and down conversions. Such transceivers are, however, sensitive to mismatches between the I and Q branches. These mismatches are unavoidable in any practical implementation, and result in finite attenuation of the mirror frequencies. In addition to the mirror-frequency interference problem, I/Q mismatches can severely compromise the performance of power amplifier linearization techniques based on pre-distortion. The effects of these impairments are becoming more pronounced as higher order modulated waveforms and/or more wideband multichannel signals are used. This brief focuses on digital-signal-processor-based I/Q mismatch calibration in wideband direct-conversion transmitters, assuming the challenging case of frequency-dependent I/Q mismatch. First, a novel widely linear (WL) calibration structure is introduced, suitable for frequency-dependent calibration. Then, two alternative principles for calibration parameter estimation are proposed. The first estimation approach stems from second-order statistics of complex communication signals, while the second technique is based on WL least-squares model fitting. Both estimators are shown by simulations to yield very good calibration performance. The obtainable performance is further assessed using laboratory RF signal measurements.     

用于带有片上时钟的窄带低中频接收机的自适应数字校准技术

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.     

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12μs only with a reference clock of 100 MHz.     

An adaptive matched filter that compensates for I,Q mismatch errors

An approach to adaptively match filter the I and Q components of complex-valued inputs consisting of a desired signal embedded in correlated external noise is presented. This approach is tolerant of I,Q mismatch errors, i.e., the external noise is effectively rejected and the desired signal enhanced in the presence of significant receiver I,Q errors. I,Q adaptive weighting removes many of the deleterious effects of I,Q quadrature detection imbalance, which can severely limit the adaptive matched filter (AMF) performance. However, for the I,Q AMF, the unknown desired signal's initial phase complicates the design procedure and even for a reasonable design criterion, the AMF performance can fluctuate significantly as a function of this phase. An I,Q AMF technique whose performance is almost phase invariant is developed, and example of its utility is shown     

3‐Level Envelope Delta‐Sigma Modulation RF Signal Generator for High‐Efficiency Transmitters

This paper presents a 0.13 μm CMOS 3‐level envelope delta‐sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz‐centered fully symmetrical 3‐level EDSM signal for high‐efficiency power amplifier architectures. It consists of an I‐Q phase modulator, a Class B wideband buffer, an up‐conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3‐state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second‐order BPF as its load to provide enough bandwidth. To achieve an accurate 3‐state envelope level in the up‐mixer output, the LO bias level is optimized. The I‐Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I‐Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of –1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.     

正交调制器载波I/Q幅相失配对TCM-8PSK性能影响

论文首先介绍了高速调制解调器中正交调制器载波I/Q支路幅相失配的模型,然后在此模型上推导了TCM-8PSK信号误比特率性能公式,最后运用Matlab中的动态仿真工具Simulink仿真验证了推导结果。推导与仿真结果都表明,在载波I/Q幅相失配条件下TCM-8PSK信号的误比特率性能下降了。     

UWB Gilbert downconverter utilising a wideband LR-CR quadrature generator

An ultra-wideband (UWB) I/Q downconverter with an LR-CR quadrature generator is demonstrated using 0.35 μm SiGe HBT technology. The I/Q outputs of this generator are always in quadrature phase at any frequency while the BJT-type active mixer inherently tolerates much LO power difference for a flat gain response. Consequently, the amplitude imbalance and phase error of the I/Q outputs are less than 1 dB and 2° in the RF frequency range 3?11 GHz.     

A Complex Image Rejection Circuit With Sign Detection Only

In direct-conversion receivers, radio frequency (RF) signals are down-converted to low or zero intermediate frequency (IF) using complex in-phase and quadrature (I/Q) mixers with no prior image filtering. Due to I/Q path gain and phase errors, image leaks into the signal band during the down-conversion process. A generic image rejection algorithm is proposed to reject image in the baseband using a zero-forcing sign-sign adaptive feedback concept. The orthonormal property of complex I/Q channels is exploited to update their gain and phase errors by detecting only four signs, and image is corrected with four multiplications and two additions. The proposed image rejection algorithm can be implemented in a digital, analog, or hybrid form. A complex baseband sample and hold (S/H) with a digital error detector, which is a hybrid example, achieves an image rejection of 65 dB while sampling at 40 MS/s. The prototype chip fabricated in 0.18-mum CMOS occupies 800times450 mum², and consumes 23 mW at 1.8 V     

A subharmonically injected LC delay line oscillator for 17-GHz quadrature LO generation

An injection-locked delay line oscillator multiplies a 5-6-GHz input by 3 to generate I/Q LO signals for 17-GHz wireless networking applications. I/Q errors caused by asymmetric injection are minimized by symmetric injection via a passive polyphase prefilter. Passive delay lines set the measured free-running frequency of the LC ring oscillator to 16.24 GHz. The measured locking range for a 0 dBm (50 /spl Omega/) input is 14.6-17.86 GHz. Input-to-output phase noise degradation is negligible, and I/Q amplitude and phase errors are <0.17 dB and <2/spl deg/, respectively. Power consumption of the 1.2/spl times/1.4 mm/sup 2/ 0.2 /spl mu/m SiGe BiCMOS testchip (excluding buffers) is 22 mW at 2.2 V.